| Electronic Components Datasheet Search |
|
SPC584BX Datasheet(PDF) 62 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
SPC584BX Datasheet(HTML) 62 Page - STMicroelectronics |
|
62 / 142 page ![]() Electrical characteristics SPC584Bx 62/142 DS11701 Rev 4 PERREF SR T Input reference clock jitter (peak to peak) Single period, fRF_REF =20 MHz —— 350 ps T Long term, fRF_REF =20 MHz -500 — 500 ps PEREYE CC T Output Eye Jitter (peak to peak)(5) —— — 400 ps 1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1. 3. The 320 MHz frequency is achieved with a 20 MHz reference clock. 4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit). 5. Measured at the transmitter output across a 100 termination resistor on a device evaluation board. See Figure 12. Table 31. LFAST PLL electrical characteristics(1) (continued) Symbol C Parameter Conditions Value Unit Min Typ Max |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |