SPC584BX datasheet(75/142 Pages) STMICROELECTRONICS

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DS11701 Rev 4

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SPC584Bx

Electrical characteristics

tfferase

Full flash erasing time(9)

9.9

18.1

23.3

14.3

—

tESRT

Erase suspend request

rate(10)

200

—

— µs

tPSRT

Program suspend request

rate(10)

—

— µs

tAMRT

Array Integrity Check - Margin

Read suspend request rate

—

— µs

tPSUS

Program suspend latency(11)

——

—

µs

tESUS

Erase suspend latency(11)

——

—

µs

tAIC0S

Array Integrity Check (2.0 MB,

sequential)(12)

12.8

—

— ms

tAIC256KS

Array Integrity Check (256

KB, sequential)(12)

1.5

—

— ms

tAIC0P

Array Integrity Check (2.0 MB,

proprietary)(12)

4.0

—

tMR0S

Margin Read (2.0 MB,

sequential)(12)

—

— ms

tMR256KS

Margin Read (256 KB,

sequential)(12)

4.0

—

— ms

1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column.

2. Actual hardware operation times; this does not include software overhead.

3. Typical program and erase times assume nominal supply values and operation at 25 °C.

4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.

Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but

not tested.

5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified

number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.

6. Initial factory condition: < 100 program/erase cycles, 25 °C typical junction temperature and nominal (± 5 %) supply

voltages.

7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for

less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature and nominal (± 5 %) supply

voltages.

8. Rate computed based on 256 KB sectors.

9. Only code sectors, not including EEPROM.

10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the

table is calculated at max frequency.

Table 40. Flash memory program and erase specifications (continued)

Symbol

Characteristics(1)(2)

Value

Unit

Typ(3) C

Initial max

Typical

end of

life(4)

Lifetime

max(5)

25 °C

(6)

All

temp

(7)

< 1 K

cycles

< 250 K

cycles

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