SPC584BX datasheet(11/142 Pages) STMICROELECTRONICS

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DS11701 Rev 4

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SPC584Bx

Description

2.3

Features overview

On-chip modules within SPC584Bx include the following features:



One main CPU, dual issue, 32-bit CPU core complexes (e200z4)

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Power Architecture embedded specification compliance

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Instruction set enhancement allowing variable length encoding (VLE), encoding a

mix of 16-bit and 32-bit instructions, for code size footprint reduction

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Single-precision floating point operations

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64 KB local data RAM for Core_2

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8 KB I-Cache and 4 KB D-Cache for Core_2



2112 KB (2048 KB code flash + 64 KB data flash) on-chip flash memory

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Supports read during program and erase operations, and multiple blocks allowing

EEPROM emulation



176 KB HSM dedicated flash memory (144 KB code + 32 KB data)



128 KB on-chip general-purpose SRAM (+ 64 KB local data RAM: 64 KB included in

the CPU)



Multi channel direct memory access controllers

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32 eDMA channels



One interrupt controller (INTC)



Dual phase-locked loops with stable clock domain for peripherals and FM modulation

domain for computational shell



Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from

multiple bus masters with end-to-end ECC



Hardware security module (HSM) with HW cryptographic co-processor



System integration unit lite (SIUL)



Boot assist Flash (BAF) supports factory programming using a serial bootload through

the asynchronous CAN or LIN/UART.



Hardware support for safety ASIL-B level related applications



Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with

16-bit counter resolution

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Buffered updates

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Support for shifted PWM outputs to minimize occurrence of concurrent edges

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Supports configurable trigger outputs for ADC conversion for synchronization to

channel output waveforms

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Shared or independent time bases

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DMA transfer support available



Body Cross Triggering Unit (BCTU)

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Triggers ADC conversions from any eMIOS channel

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Triggers ADC conversions from up to 2 dedicated PIT_RTIs

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One event configuration register dedicated to each timer event allows to define the

corresponding ADC channel

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Synchronization with ADC to avoid collision



Enhanced analog-to-digital converter system with:

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Two independent fast 12-bit SAR analog converters

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