ADM1027 datasheet(3/56 Pages) AD

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REV. A

ADM1027

–3–

Parameter

Min

Typ

Max

Unit

Test Conditions/Comment

OPEN-DRAIN SERIAL DATA BUS

OUTPUT (SDA)

Output Low Voltage, VOL

0.4

IOUT = –4.0 mA, VCC = 3.3 V

High Level Output Current, IOH

0.1

mAVOUT = VCC

SMBUS DIGITAL INPUTS

(SCL, SDA)

Input High Voltage, VIH

2.0

Input Low Voltage, VIL

0.4

Hysteresis

500

DIGITAL INPUT LOGIC LEVELS

(VID0–4)

Input High Voltage, VIH

1.7

Input Low Voltage, VIL

0.8

DIGITAL INPUT LOGIC LEVELS

(TACH INPUTS)

Input High Voltage, VIH

2.0

5.5

Maximum Input Voltage

Input Low Voltage, VIL

0.8

–0.3

Minimum Input Voltage

Hysteresis

0.5

V p-p

DIGITAL INPUT CURRENT

Input High Current, IIH

–1

mAVIN = VCC

Input Low Current, IIL

mAVIN = 0

Input Capacitance, CIN

5pF

SERIAL BUS TIMING

Clock Frequency, fSCLK

100

kHz

See Figure 1

Glitch Immunity, tSW

See Figure 1

Bus Free Time, tBUF

4.7

See Figure 1

Start Setup Time, tSU;STA

4.7

See Figure 1

Start Hold Time, tHD;STA

4.0

See Figure 1

SCL Low Time, tLOW

4.7

See Figure 1

SCL High Time, tHIGH

4.0

See Figure 1

SCL, SDA Rise Time, tr

1000

See Figure 1

SCL, SDA Fall Time, tf

300

See Figure 1

Data Setup Time, tSU;DAT

250

See Figure 1

Data Hold Time, tHD;DAT

300

See Figure 1

Detect Clock Low Timeout, tTIMEOUT

Can Be Optionally Disabled

NOTES

1All voltages are measured with respect to GND, unless otherwise specified.

2Typicals are at T

A = 40

∞C and represent the most likely parametric norm.

3Logic inputs will accept input high voltages up to V

MAX even when the device is operating down to V MIN.

4Timing specifications are tested at logic levels of V

IL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.

Specifications subject to change without notice.

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