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CS47L85 Datasheet(PDF) 188 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 188 Page - Cirrus Logic

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CS47L85
188
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
me_Ctrl_2
7:0
AIF3RX_SLOT_L
EN [7:0]
18h
AIF3 RX Slot Length
(Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
R1417
(0589h)
AIF3_Fra
me_Ctrl_3
5:0
AIF3TX1_SLOT
[5:0]
0h
AIF3 TX Channel 1 Slot position
Defines the TX timeslot position of the
Channel 1 audio sample
Integer (LSB=1); Valid from 0 to 63
R1418
(058Ah)
AIF3_Fra
me_Ctrl_4
5:0
AIF3TX2_SLOT
[5:0]
1h
AIF3 TX Channel 2 Slot position
Defines the TX timeslot position of the
Channel 2 audio sample
Integer (LSB=1); Valid from 0 to 63
R1425
(0591h)
AIF3_Fra
me_Ctrl_1
1
5:0
AIF3RX1_SLOT
[5:0]
0h
AIF3 RX Channel 1 Slot position
Defines the RX timeslot position of the
Channel 1 audio sample
Integer (LSB=1); Valid from 0 to 63
R1426
(0592h)
AIF3_Fra
me_Ctrl_1
2
5:0
AIF3RX2_SLOT
[5:0]
1h
AIF3 RX Channel 2 Slot position
Defines the RX timeslot position of the
Channel 2 audio sample
Integer (LSB=1); Valid from 0 to 63
Table 51 AIF3 Digital Audio Data Control
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1444
(05A4h)
AIF4_For
mat
2:0
AIF4_FMT [2:0]
000
AIF4 Audio Interface Format
000 = DSP Mode A
001 = DSP Mode B
010 = I2S mode
011 = Left Justified mode
Other codes are Reserved
This field is locked when AIF4 channels
are enabled; it can only be changed when
all AIF4 channels are disabled.
R1447
(05A7h)
AIF4_Fra
me_Ctrl_1
13:8
AIF4TX_WL [5:0]
18h
AIF4 TX Word Length
(Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
7:0
AIF4TX_SLOT_L
EN [7:0]
18h
AIF4 TX Slot Length
(Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
R1448
(05A8h)
AIF4_Fra
me_Ctrl_2
13:8
AIF4RX_WL [5:0]
18h
AIF4 RX Word Length
(Number of valid data bits per slot)
Integer (LSB = 1); Valid from 16 to 32
7:0
AIF4RX_SLOT_L
EN [7:0]
18h
AIF4 RX Slot Length
(Number of BCLK cycles per slot)
Integer (LSB = 1); Valid from 16 to 128
R1449
(05A9h)
AIF4_Fra
me_Ctrl_3
5:0
AIF4TX1_SLOT
[5:0]
0h
AIF4 TX Channel 1 Slot position
Defines the TX timeslot position of the
Channel 1 audio sample
Integer (LSB=1); Valid from 0 to 63
R1450
(05AAh)
AIF4_Fra
me_Ctrl_4
5:0
AIF4TX2_SLOT
[5:0]
1h
AIF4 TX Channel 2 Slot position
Defines the TX timeslot position of the
Channel 2 audio sample
Integer (LSB=1); Valid from 0 to 63



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