CS47L85 datasheet(189/370 Pages) CIRRUS

189 / 370 page

CS47L85

Rev 4.3

189

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1457

(05B1h)

AIF4_Fra

me_Ctrl_1

5:0

AIF4RX1_SLOT

[5:0]

AIF4 RX Channel 1 Slot position

Defines the RX timeslot position of the

Channel 1 audio sample

Integer (LSB=1); Valid from 0 to 63

R1458

(05B2h)

AIF4_Fra

me_Ctrl_1

5:0

AIF4RX2_SLOT

[5:0]

AIF4 RX Channel 2 Slot position

Defines the RX timeslot position of the

Channel 2 audio sample

Integer (LSB=1); Valid from 0 to 63

Table 52 AIF4 Digital Audio Data Control

AIF TDM AND TRI-STATE CONTROL

The AIFn output pins are tri-stated when the AIFn_TRI register is set. Note that this function only affects output pins that

have been configured for the respective AIFn function. Any GPIO pin that is configured for a different function will not be

affected by the AIFn_TRI register.

See “General Purpose Input / Output” to configure the GPIO pins.

Under default conditions, the AIFnTXDAT output is held at logic 0 when the CS47L85 is not transmitting data (i.e., during

timeslots that are not enabled for output by the CS47L85). When the AIFnTX_DAT_TRI register is set, the CS47L85 tri-

states the respective AIFnTXDAT pin when not transmitting data, allowing other devices to drive the AIFnTXDAT connection.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1281

(0501h)

AIF1_Tx_

Pin_Ctrl

AIF1TX_DAT_TR

AIF1TXDAT Tri-State Control

0 = Logic 0 during unused timeslots

1 = Tri-stated during unused timeslots

R1283

(0503h)

AIF1_Rate

_Ctrl

AIF1_TRI

AIF1 Audio Interface Tri-State Control

0 = Normal

1 = AIF1 Outputs are tri-stated

Note that this bit only affects output pins

that have been configured for the

respective AIF1 function.

Table 53 AIF1 TDM and Tri-State Control

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1345

(0541h)

AIF2_Tx_

Pin_Ctrl

AIF2TX_DAT_TR

AIF2TXDAT Tri-State Control

0 = Logic 0 during unused timeslots

1 = Tri-stated during unused timeslots

R1347

(0543h)

AIF2_Rate

_Ctrl

AIF2_TRI

AIF2 Audio Interface Tri-State Control

0 = Normal

1 = AIF2 Outputs are tri-stated

Note that this bit only affects output pins

that have been configured for the

respective AIF2 function.

Table 54 AIF2 TDM and Tri-State Control

CS47L85 Datasheet(PDF) 189 Page - Cirrus Logic

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