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CS47L85 Datasheet(PDF) 191 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 191 Page - Cirrus Logic

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CS47L85
Rev 4.3
191
SLIMBUS INTERFACE
The SLIMbus protocol is highly configurable and adaptable, supporting multiple audio signal paths, and mixed sample rates
simultaneously. It also supports control messaging and associated communications between devices.
SLIMBUS DEVICES
The SLIMbus components comprise different device classes (Manager, Framer, Interface, Generic). Each component on
the bus has an Interface Device, which provides bus management services for the respective component. One or more
components on the bus will provide Manager and Framer Device functions; the Manager has the capabilities to administer
the bus, whilst the Framer is responsible for driving the CLK line and for driving the DATA required to establish the Frame
Structure on the bus. Note that only one Manager and one Framer Device will be active at any time. The Framer function
can be transferred between Devices when required. Generic Devices provide the basic SLIMbus functionality for the
associated Port(s), and for the Transport Protocol by which audio signal paths are established on the bus.
SLIMBUS FRAME STRUCTURE
The SLIMbus bit stream is formatted within a defined structure of Cells, Slots, Subframes, Frames, and Superframes:
A single data bit is known as a Cell
4 Cells make a Slot
192 Slots make a Frame
8 Frames make a Superframe
The bit stream structure is configurable to some extent, but the Superframe definition always comprises 1536 slots. The
transmitted/received bit rate is not fixed; it can be configured according to system requirements, and can be changed
dynamically without interruption to active audio paths.
The SLIMbus CLK frequency (also the bus bit rate) is defined by a Root Frequency (RF) and a Clock Gear (CG). In the top
Clock Gear (Gear 10), the CLK frequency is equal to the Root Frequency. Each reduction in the Clock Gear halves the CLK
frequency, and doubles the duration of the Superframe.
The SLIMbus bandwidth will typically comprise Control space (for bus messages, synchronisation etc.) and Data space (for
audio paths). The precise allocation is configurable, and can be entirely Control space, if required.
The Subframe definition comprises the number of Slots per Subframe (6, 8, 24 or 32 Slots), and the number of these Slots
(per Subframe) allocated as Control space. The applicable combination of Subframe length and Control space width are
defined by the Subframe Mode (SM) parameter.
The SLIMbus Frame always comprises 192 Slots, regardless of the Subframe definition. A number of Slots are allocated to
Control space, as noted above; the remaining Slots are allocated to Data space. Some of the Control space is required for
Framing Information and for the Guide Channel (described below); the remainder of the Control space are allocated to the
Message Channel.
CONTROL SPACE
Framing Information is provided in Slots 0 and 96 of every Frame. Slot 0 contains a 4-bit synchronisation code; Slot 96
contains the 32-bit Framing Information, transmitted 4 bits at a time over the 8 Frames that make up the SLIMbus Superframe.
The Clock Gear, Root Frequency, Subframe configuration, along with some other parameters, are encoded within the
Framing Information.
The Guide Channel occupies two Slots within Frame 0. This provides the necessary information for a SLIMbus component
to acquire and verify the frame synchronisation. The Guide Channel occupies the first two Control space Slots within the
first Frame of the bit stream, excluding the Framing Information Slots. Note that the exact Slot allocation will depend upon
the applicable Subframe mode.
The Message Channel is allocated all of the Control space not used by the Framing Information or the Guide Channel. The
Message Channel enables SLIMbus devices to communicate with each other, using a priority-based mechanism defined in
the MIPI specification.
Messages may be broadcast to all devices on the bus, or can be addressed to specific devices using their allocated Logical
Address (LA) or Enumeration Address (EA). Note that, device-specific messages are directed to a particular device (i.e.,
Manager, Framer, Interface or Generic) within a component on the bus.



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