CS47L85 datasheet(206/370 Pages) CIRRUS

206 / 370 page

CS47L85

206

Rev 4.3

OUTPUT SIGNAL PATH ENABLE

The output signal paths are enabled using the register bits described in Table 71. The respective bit(s) must be enabled for

analogue or digital output on the respective output path(s).

The output signal paths are muted by default. It is recommended that de-selecting the mute should be the final step of the

path enable control sequence. Similarly, the mute should be selected as the first step of the path disable control sequence.

The output signal path mute functions are controlled using the register bits described in Table 76.

The supply rails for outputs (OUT1, OUT2 and OUT3) are generated using an integrated dual-mode Charge Pump, CP1.

The Charge Pump is enabled automatically by the CS47L85

when required by the output drivers. See the “Charge Pumps,

Regulators and Voltage Reference

” section for further details.

The CS47L85 schedules a pop-suppressed control sequence to enable or disable the OUT1, OUT2 OUT3 and OUT4 signal

paths. This is automatically managed in response to setting the respective HPnx_ENA or SPKOUTx_ENA register bits. See

“Control Write Sequencer” for further details.

The output signal path enable/disable control sequences are inputs to the Interrupt circuit, and can be used to trigger an

Interrupt event when a sequence completes. See “Interrupts” for further details.

The system clock, SYSCLK, must be configured and enabled before any audio path is enabled. The output signal paths

should be kept disabled (HPnx_ENA=0, SPKOUTx_ENA=0, OUTnx_ENA=0) if SYSCLK is not enabled. The ASYNCCLK

y also be required, depending on the path configuration. See “Clocking and Sample Rates” for details of the system

clocks (including requirements for reconfiguring SYSCLK while audio paths are enabled).

The CS47L85 performs automatic checks to confirm that the SYSCLK frequency is high enough to support the output signal

paths and associated DACs. If an attempt is made to enable an output signal path, and there are insufficient SYSCLK cycles

to support it, then the attempt will be unsuccessful. (Note that any signal paths that are already active will not be affected

under these circumstances.)

The status bits in Register R1025 and R1030 indicate the status of each of the output signal paths. If an Underclocked Error

condition occurs, then these bits provide readback of which signal path(s) have been successfully enabled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R1024

(0400h)

Output_En

ables_1

OUT6L_ENA

Output Path 6 (Left) Enable

0 = Disabled

1 = Enabled

OUT6R_ENA

Output Path 6 (Right) Enable

0 = Disabled

1 = Enabled

OUT5L_ENA

Output Path 5 (Left) Enable

0 = Disabled

1 = Enabled

OUT5R_ENA

Output Path 5 (Right) Enable

0 = Disabled

1 = Enabled

SPKOUTL_ENA

Output Path 4 (Left) Enable

0 = Disabled

1 = Enabled

SPKOUTR_ENA

Output Path 4 (Right) Enable

0 = Disabled

1 = Enabled

HP3L_ENA

Output Path 3 (Left) Enable

0 = Disabled

1 = Enabled

HP3R_ENA

Output Path 3 (Right) Enable

0 = Disabled

1 = Enabled

HP2L_ENA

Output Path 2 (Left) Enable

0 = Disabled

1 = Enabled

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