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CS47L85 Datasheet(PDF) 203 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 203 Page - Cirrus Logic

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CS47L85
Rev 4.3
203
CLOCK GEAR
DESCRIPTION
SLIMCLK FREQUENCY
(
assuming 24.576MHz Root Frequency)
10
Divide by 1
24.576MHz
9
Divide by 2
12.288MHz
8
Divide by 4
6.144MHz
7
Divide by 8
3.072MHz
6
Divide by 16
1.536MHz
5
Divide by 32
768kHz
4
Divide by 64
384kHz
3
Divide by 128
192kHz
2
Divide by 256
96kHz
1
Divide by 512
48kHz
Table 68 SLIMbus Clock Gear Selection
When the CS47L85 is the active Framer, the SLIMCLK output is synchronised to the SYSCLK or ASYNCCLK system clock,
as selected by the SLIMCLK_SRC register bit.
The applicable system clock must be enabled, and configured at the SLIMbus Root Frequency, whenever the CS47L85 is
the active Framer. The system clock must not be interrupted or reconfigured if the CS47L85 is the active Framer. See
“Clocking and Sample Rates” for details of the SYSCLK and ASYNCCLK system clocks.
When the CS47L85 is not configured as the active Framer device, then the SLIMCLK input can be used to provide a
reference source for the Frequency Locked Loops (FLLs). The frequency of this reference is controlled using the
SLIMCLK_REF_GEAR register, as described in Table 69.
The SLIMbus clock reference is generated using an adaptive divider on the SLIMCLK input. The divider automatically adapts
to the SLIMbus Clock Gear (CG).
Note that, if the Clock Gear (CG) on the bus is lower than the SLIMCLK_REF_GEAR, then the selected reference frequency
cannot be supported, and the SLIMbus clock reference is disabled.
The SLIMbus
clock reference is selected as input to the FLLs using the FLLn_REFCLK_SRC registers. See “Clocking and
Sample Rates
” for details of system clocking and the FLLs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1507
(05E3h)
SLIMbus_
Framer_R
ef_Gear
4
SLIMCLK_SRC
0
SLIMbus Clock source
Selects the SLIMbus reference clock in
Active Framer mode.
0 = SYSCLK
1 = ASYNCCLK
Note that the applicable clock must be
enabled, and configured at the SLIMbus
Root Frequency, in Active Framer mode.
3:0
SLIMCLK_REF_
GEAR [3:0]
4h
SLIMbus Clock Reference control.
Sets the SLIMbus reference clock relative
to the SLIMbus Root Frequency (RF).
0h = Clock stopped
1h = Gear 1 (RF / 512)
2h = Gear 2 (RF / 256)
3h = Gear 3 (RF / 128)
4h = Gear 4 (RF / 64)
5h = Gear 5 (RF / 32)
6h = Gear 6 (RF / 16)
7h = Gear 7 (RF / 8)
8h = Gear 8 (RF / 4)
9h = Gear 9 (RF / 2)
Ah = Gear 10 (RF)
All other codes are Reserved
Table 69 SLIMbus Clock Reference Control



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