CS47L85 datasheet(329/370 Pages) CIRRUS

329 / 370 page

CS47L85

Rev 4.3

329

DRC SIGNAL DETECT SEQUENCES

The Dynamic Range Control (DRC) function within the CS47L85 Digital Core provides a configurable signal detect function.

This allows the signal level at the DRC input to be monitored and used to trigger other events.

The DRC Signal Detect functions are enabled and configured using the register fields described in Table 14 and Table 15

for DRC1 and DRC2 respectively.

A Control Write Sequence can be associated with a rising edge and/or a falling edge of the DRC1 Signal Detect output. This

is enabled using the DRC1_WSEQ_SIG_DET_ENA register bit, as described in Table 14.

Note that signal detection is supported on DRC1 and DRC2, but the triggering of the Control Write Sequencer is available

on DRC1 only.

When the DRC Signal Detect sequence is enabled, the Control Write Sequencer will be triggered whenever the DRC1 Signal

Detect output transitions (high or low). The applicable start index location within the sequencer memory is separately

configurable for each logic condition.

The WSEQ_DRC1_SIG_DET_RISE_SEQ_INDEX register defines the sequencer start index corresponding to a DRC1

Signal Detect Rising Edge event, as described in Table 121. The WSEQ_DRC1_SIG_DET_FALL_SEQ_INDEX register

defines the sequencer start index corresponding to a DRC1 Signal Detect Falling Edge event.

Note that a sequencer start index of 1FFh will cause the respective sequence to be aborted.

The DRC Signal Detect sequences cannot be independently enabled for rising and falling edges. Instead, a start index of

1FFh can be used to disable the sequence for either edge, if required.

The DRC Signal Detect control sequences are undefined following Power-On Reset (POR), Hardware Reset, or following a

Sleep mode transition. The DRC Signal Detect control sequences must be reconfigured by the host processor following any

of these events. Note that all control sequences are maintained in the sequencer memory through Software Reset.

See “Digital Core” for further details of the Dynamic Range Control (DRC) function.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R110

(006Eh)

Trigger_Seq

uence_Sele

ct_32

8:0

WSEQ_DRC1_SI

G_DET_RISE_IN

DEX [8:0]

1FFh

DRC1 Signal Detect (Rising) Write

Sequence start index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with DRC1 Signal Detect (Rising)

detection.

Valid from 0 to 507 (1FBh).

R111

(006Fh)

Trigger_Seq

uence_Sele

ct_33

8:0

WSEQ_DRC1_SI

G_DET_FALL_IN

DEX [8:0]

1FFh

DRC1 Signal Detect (Falling) Write

Sequence start index

This field contains the index location in

the sequencer memory of the first

command in the sequence associated

with DRC1 Signal Detect (Falling)

detection.

Valid from 0 to 507 (1FBh).

Table 121 Write Sequencer Control - DRC Signal Detect

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