CS47L85 datasheet(333/370 Pages) CIRRUS

333 / 370 page

CS47L85

Rev 4.3

333

PROGRAMMING A SEQUENCE

A Control Write Sequence comprises a series of write operations to data bits (or groups of bits) within the control register

map. Each write operation is defined by 5 fields, as described below.

The block of 2 registers is replicated 508 times, defining each of the sequencer’s 508 possible index addresses. Many

sequences can be stored in the sequencer memory at the same time, with each assigned a unique range of index addresses.

The WSEQ_DELAYn register is used to identify the ‘end of sequence’ position, as described below.

Note that, in the following descriptions, the

term ‘n’ denotes the sequencer index address (valid from 0 to 507).

WSEQ_DATA_WIDTHn is a 3-bit field which identifies the width of the data block to be written. Note that the maximum value

of this field selects a width of 8-bits; writing to register fields greater than 8 bits wide must be performed using two separate

operations of the Write Sequencer.

WSEQ_ADDRn is a 13-bit field containing the register address in which the data should be written.

WSEQ_DELAYn is a 4-bit field which controls the waiting time between the current step and the next step in the sequence

(i.e., the delay occurs after the write in which it was called). The total delay time per step (including execution) is defined

below, giving a useful range of execution/delay times from 3.3

s up to 1s per step. Setting this field to 0xF identifies the step

as the last in the sequence.

If WSEQ_DELAYn = 0h or Fh, the step execution time is 3.3µs

For all other values, the step execution time is 61.44µs x ((2 WSEQ_DELAY ) - 1)

WSEQ_DATA_STARTn is a 4-bit field which identifies the LSB position within the selected control register to which the data

should be written. For example, setting WSEQ_DATA_STARTn = 0100 will select bit 4 as the LSB position of the data to be

written.

WSEQ_DATAn is an 8-bit field which contains the data to be written to the selected control register. The

WSEQ_DATA_WIDTHn field determines how many of these bits are written to the selected control register; the most

significant bits (above the number indicated by WSEQ_DATA_WIDTHn) are ignored.

The register definitions for Step 0 are described in Table 126. The equivalent definitions also apply to Step 1 through to Step

507, in the subsequent register address locations.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R12288

(3000h)

WSEQ_Sequ

ence_1

31:29

WSEQ_DATA_

WIDTH0 [2:0]

000

Width of the data block written in this

sequence step.

000 = 1 bit

001 = 2 bits

010 = 3 bits

011 = 4 bits

100 = 5 bits

101 = 6 bits

110 = 7 bits

111 = 8 bits

28:16

WSEQ_ADDR0

[12:0]

0000h

Control Register Address to be

written to in this sequence step.

15:12

WSEQ_DELAY0

[3:0]

0000

Time delay after executing this step.

00h = 3.3us

01h to 0Eh = 61.44us x

((2^WSEQ_DELAY)-1)

Fh = End of sequence marker

11:8

WSEQ_DATA_S

TART0 [3:0]

0000

Bit position of the LSB of the data

block written in this sequence step.

0000 = Bit 0

…

1111 = Bit 15

CS47L85 Datasheet(PDF) 333 Page - Cirrus Logic

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