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CS47L85 Datasheet(PDF) 335 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 335 Page - Cirrus Logic

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CS47L85
Rev 4.3
335
CHARGE PUMPS, REGULATORS AND VOLTAGE REFERENCE
The CS47L85 incorporates two Charge Pump circuits and two LDO Regulator circuits to generate supply rails for internal
functions and to support external microphone requirements. The CS47L85 also provides four MICBIAS generators which
provide low noise reference voltages suitable for biasing electret condenser (ECM) type microphones or powering digital
microphones.
Refer to the
“Applications Information” section for recommended external components.
The CPVDD domain (1.8V) powers the Charge Pump 1 and Charge Pump 2 circuits. The CPVDD2 power domain (1.2V) is
an additional supply used by Charge Pump 1 only.
The DCVDD domain (1.2V) can be supplied externally, or can be provided by the LDO1 Regulator.
Note that the CPVDD2 domain must always be powered externally; the CPVDD2 domain should not be connected to the
LDO1 output.
CHARGE PUMPS AND LDO2 REGULATOR
Charge Pump 1 (CP1) is used to generate the positive and negative supply rails for the analogue output drivers. CP1 is
enabled automatically by the CS47L85 when required by the output drivers.
Charge Pump 2 (CP2) powers LDO2, which provides the supply rail for analogue input circuits and for the MICBIAS
generators. CP2 and LDO2 are enabled using the CP2_ENA register bit.
The 32kHz clock must be configured and enabled when using CP2. See “Clocking and Sample Rates” for details of the
system clocks.
When CP2 and LDO2 are enabled, the MICVDD voltage can be selected using the LDO2_VSEL control field. Note that,
when one or more of the MICBIAS generators is operating in normal (regulator) mode, then the MICVDD voltage must be
at least 200mV greater than the highest selected MICBIASn output voltage(s).
When CP2 and LDO2 are enabled, an internal bypass path may be selected, connecting the MICVDD pin directly to the
CPVDD supply. This path is controlled using the CP2_BYPASS register. Note that the bypass path is only supported when
CP2 is enabled.
When CP2 is disabled, the CP2VOUT pin can be configured to be floating or to be actively discharged. This is selected
using the CP2_DISCH register bit.
When LDO2 is disabled, the MICVDD pin can be configured to be floating or to be actively discharged. This is selected using
the LDO2_DISCH register bit.
The MICVDD pin is connected to the output of LDO2. Note that the MICVDD does not support direct connection to an
external supply; MICVDD is always powered internally to the CS47L85.
The Charge Pumps and LDO2 Regulator circuits are illustrated in Figure 86. The associated register control bits are
descrbed in Table 129.
Note that decoupling capacitors and flyback capacitors are required for these circuits. Refer to the “Applications Information”
section for recommended external components.
MICROPHONE BIAS (MICBIAS) CONTROL
There are four MICBIAS generators which provide low noise reference voltages suitable for biasing electret condenser (ECM)
type microphones or powering digital microphones. Refer to the
“Applications Information” section for recommended external
components.
The MICBIAS generators are powered from MICVDD, which is generated by an internal Charge Pump and LDO, as
illustrated in Figure 86.
The MICBIAS outputs can be independently enabled using the MICBn_ENA register bits (where n = 1, 2 3 or 4 for MICBIAS1,
2, 3 or 4 respectively).
When a MICBIAS output is disabled, the output pin can be configured to be floating or to be actively discharged. This is
selected using the MICBn_DISCH register bits.
The MICBIAS generators can each operate as a voltage regulator or in bypass mode. The applicable mode is selected using
the MICBn_BYPASS registers.
In Regulator mode (MICBn_BYPASS=0), the output voltage is selected using the MICBn_LVL register bits. In this mode,
MICVDD must be at least 200mV greater than the required MICBIAS output voltages. The MICBIAS outputs are powered



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