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CS47L85 Datasheet(PDF) 337 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 337 Page - Cirrus Logic

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CS47L85
Rev 4.3
337
BLOCK DIAGRAM AND CONTROL REGISTERS
The Charge Pump and Regulator circuits are illustrated in Figure 86. Note that decoupling capacitors and flyback capacitors
are required for these circuits. Refer to the “Applications Information” section for recommended external components.
Analogue output
supply
CPVDD
CPGND
AGND
LDO 1
LDOVDD
LDOENA
Digital Core supply
LDOVOUT
DGND
Analogue reference
LDO1_VSEL[5:0]
LDO1_DISCH
LDO1ENA_PD
LDO1ENA_PU
MICBIAS2
MICBIAS1
MICB1_ENA
MICB1_BYPASS
MICB1_LVL[3:0]
MICB1_RATE
MICB1_DISCH
MICB1_EXT_CAP
MICB2_ENA
MICB2_BYPASS
MICB2_LVL[3:0]
MICB2_RATE
MICB2_DISCH
MICB2_EXT_CAP
MICBIAS3
MICB3_ENA
MICB3_BYPASS
MICB3_LVL[3:0]
MICB3_RATE
MICB3_DISCH
MICB3_EXT_CAP
DCVDD
LDO2_VSEL[5:0]
LDO2_DISCH
CP2CA
CP2VOUT
CP2CB
Charge Pump 1
CP2_ENA
CP2_BYPASS
CP2_DISCH
LDO1 may be used to generate the DCVDD
supply. In this case, the LDOVOUT pin must
be connected to the DCVDD pin.
Analogue input
supply
Voltage
Reference
AVDD
Analogue supply
MICVDD
MICBIAS4
MICB4_ENA
MICB4_BYPASS
MICB4_LVL[3:0]
MICB4_RATE
MICB4_DISCH
MICB4_EXT_CAP
Charge
Pump 2
LDO2
Figure 86 Charge Pumps and Regulators
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R512
(0200h)
Mic_Charg
e_Pump_1
2
CP2_DISCH
1
Charge Pump 2 Discharge
0 = CP2VOUT floating when disabled
1 = CP2VOUT discharged when disabled
1
CP2_BYPASS
1
Charge Pump 2 and LDO2 Bypass Mode
0 = Normal
1 = Bypass mode
In Bypass mode, CPVDD is connected
directly to MICVDD.
Note that CP2_ENA must also be set.
0
CP2_ENA
1
Charge Pump 2 and LDO2 Control
(Provides analogue input and MICVDD
supplies)
0 = Disabled
1 = Enabled



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