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CS47L85 Datasheet(PDF) 340 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 340 Page - Cirrus Logic

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CS47L85
340
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8:5
MICB4_LVL [3:0]
7h
Microphone Bias 4 Voltage Control
(when MICB4_BYPASS = 0)
0h = 1.5V
1h = 1.6V
… (0.1V steps)
Ch = 2.7V
Dh to Fh = 2.8V
3
MICB4_RATE
0
Microphone Bias 4 Rate (Bypass mode)
0 = Fast start-up / shut-down
1 = Pop-free start-up / shut-down
2
MICB4_DISCH
1
Microphone Bias 4 Discharge
0 = MICBIAS4 floating when disabled
1 = MICBIAS4 discharged when disabled
1
MICB4_BYPASS
1
Microphone Bias 4 Mode
0 = Regulator mode
1 = Bypass mode
0
MICB4_ENA
0
Microphone Bias 4 Enable
0 = Disabled
1 = Enabled
R6864
(1AD0h)
AOD_Pad
_Ctrl
15
LDO1ENA_PD
1
LDOENA Pull-Down Control
0 = Disabled
1 = Enabled
Note - when LDO1ENA_PD and
LDO1ENA_PU are both set to ‘1’, then a
‘bus keeper’ function is enabled on the
LDOENA pin.
14
LDO1ENA_PU
0
LDOENA Pull-Up Control
0 = Disabled
1 = Enabled
Note - when LDO1ENA_PD and
LDO1ENA_PU are both set to ‘1’, then a
‘bus keeper’ function is enabled on the
LDOENA pin.
Table 129 Charge Pump and LDO Control Registers
LDO2_VSEL [5:0]
LDO OUTPUT
LDO2_VSEL [5:0]
LDO OUTPUT
LDO2_VSEL [5:0]
LDO OUTPUT
00h
0.900V
10h
1.300V
20h
2.600V
01h
0.925V
11h
1.325V
21h
2.700V
02h
0.950V
12h
1.350V
22h
2.800V
03h
0.975V
13h
1.375V
23h
2.900V
04h
1.000V
14h
1.400V
24h
3.000V
05h
1.025V
15h
1.500V
25h
3.100V
06h
1.050V
16h
1.600V
26h
3.200V
07h
1.075V
17h
1.700V
27h
3.300V
08h
1.100V
18h
1.800V
28h to 3Fh
3.300V
09h
1.125V
19h
1.900V
0Ah
1.150V
1Ah
2.000V
0Bh
1.175V
1Bh
2.100V
0Ch
1.200V
1Ch
2.200V
0Dh
1.225V
1Dh
2.300V
0Eh
1.250V
1Eh
2.400V
0Fh
1.275V
1Fh
2.500V
Table 130 LDO2 Voltage Control



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