CS47L85 datasheet(341/370 Pages) CIRRUS

341 / 370 page

CS47L85

Rev 4.3

341

JTAG INTERFACE

The JTAG interface provides test and debug access to the CS47L85 DSP core. The interface comprises 5 pins, as detailed

below.



TCK: Clock input



TDI: Data input



TDO: Data output



TMS: Mode select input



TRST: Test Access Port reset input (active low)

For normal operation (test and debug access disabled), the JTAG interface should be held in reset (i.e., TRST should be at

logic 0). An internal pull-down resistor holds the TRST pin low when not actively driven. External connection to DGND is

recommended, if the JTAG interface function is not required.

The other JTAG input pins (TCK, TDI, TMS) should also be held at logic 0 for normal operation. An internal pull-down resistor

holds these pins low when not actively driven.

If the JTAG interface is enabled (TRST de-asserted, and TCK active) at the time of Power-On Reset, or any other Reset,

then a Software Reset must be scheduled, with the TCK input stopped or TRST asserted (logic ‘0’), before using the JTAG

interface.

As a general rule, it is recommended to always schedule a Software Reset before starting the JTAG clock, or de-asserting

the JTAG reset. In this event, the JTAG interface should be held in its reset state until the Software Reset has completed,

and the BOOT_DONE_STSx bits have been set.

See “Hardware Reset, Software Reset, Wake-Up, and Device ID” for further details of the CS47L85 Software Reset.

Note that DSPCLK must be present and enabled, if the

JTAG interface is enabled. See “Clocking and Sample Rates” for

further details of the CS47L85 system clocks.

THERMAL SHUTDOWN AND SHORT CIRCUIT PROTECTION

The CS47L85 incorporates thermal protection functions, and also provides short-circuit detection on the Class D speaker

and headphone output paths, as described below.

The temperature sensor detects when the device temperature is within normal limits or if the device is approaching a

hazardous temperature condition.

The temperature sensor is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see

“Interrupts”. A two-stage indication is provided, via the SPK_OVERHEAT_WARN_EINTn and SPK_OVERHEAT_EINTn

interrupts.

If the upper temperature threshold (SPK_OVERHEAT_EINTn) is exceeded, then the Class D speaker outputs will

automatically be disabled in order to protect the device. When the speaker driver shutdown is complete, a further interrupt,

SPK_SHUTDOWN_EINTn, will be asserted.

The short circuit detection function for the Class D speaker outputs is triggered when the respective output drivers are

enabled (using the register bits described in Table 71). If a short circuit is detected at this time, then the enable will be

unsuccessful, and the respective output driver will not be enabled.

The Class D speaker short circuit detection provides inputs to the Interrupt control circuit and can be used to trigger an

Interrupt event - see

“Interrupts”.

If the Class D speaker short circuit condition is detected, then the respective driver(s) will automatically be disabled in order

to protect the device. When the speaker driver shutdown is complete, a further interrupt, SPK_SHUTDOWN_EINTn, will be

asserted.

To enable the Class D speaker outputs following a short circuit detection, the host processor must disable and re-enable

the output driver(s). Note that the short circuit status bits will always be cleared when the drivers are disabled.

The short circuit detection function for the headphone output paths operates continuously whilst the respective output driver

is enabled. If a short circuit is detected on any headphone output, then current limiting is applied, in order to protect the

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