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CS47L85 Datasheet(PDF) 345 Page - Cirrus Logic

Part # CS47L85
Description  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Datasheet(HTML) 345 Page - Cirrus Logic

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CS47L85
Rev 4.3
345
PIN NO
NAME
TYPE
RESET STATUS
DBVDD3 power domain
M4
AIF3BCLK/GPIO24
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
K4
AIF3LRCLK/GPIO26
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
N4
AIF3RXDAT/GPIO25
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
L4
AIF3TXDAT/GPIO23
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
M7
AIF4BCLK/GPIO28
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
N8
AIF4LRCLK/GPIO30
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
P8
AIF4RXDAT/GPIO29
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
L7
AIF4TXDAT/GPIO27
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
L6
CIF3MISO
Digital Output
Digital output
N6
CIF3MOSI
Digital Input
Digital input
N7
CIF3SCLK
Digital Input
Digital input
M6
CIF3SS
¯¯¯¯¯¯
Digital Input
Digital input
J4
GPIO3
Digital Input / Output
Digital input, Bus-keeper enabled
H7
GPIO4
Digital Input / Output
Digital input, Bus-keeper enabled
G6
GPIO5
Digital Input / Output
Digital input, Bus-keeper enabled
N5
GPIO6
Digital Input / Output
Digital input, Bus-keeper enabled
H6
GPIO7
Digital Input / Output
Digital input, Bus-keeper enabled
J6
GPIO8
Digital Input / Output
Digital input, Bus-keeper enabled
M5
MIF3SCLK/GPIO13
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
L5
MIF3SDA/GPIO14
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
DBVDD4 power domain
N10
DMICCLK4/GPIO31
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
N9
DMICCLK5/GPIO33
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
L8
DMICCLK6/GPIO35
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
M9
DMICDAT4/GPIO32
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
P9
DMICDAT5/GPIO34
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
M8
DMICDAT6/GPIO36
Digital Input / Output
Digital input (GPIO), Bus-keeper enabled
Table 133 CS47L85 Digital I/O Status in Reset
Note that the dual function INnLN/DMICCLKn and INnRN/DMICDATn pins default to their respective analogue input
functions after Power-On Reset is completed. The analogue input functions are referenced to the MICVDD power domain.
The power-up condition of the GPIO pins depends upon whether the pin is actively driven by another device when the
CS47L85 starts up. If the pin is actively driven, the bus-keeper will maintain this logic level. If the pin is not actively driven,
the bus-keeper may establish either a logic 1 or logic 0 as the default input level.



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