CS47L85 datasheet(346/370 Pages) CIRRUS

346 / 370 page

CS47L85

346

Rev 4.3

HARDWARE RESET, SOFTWARE RESET, WAKE-UP, AND DEVICE ID

The CS47L85 provides a Hardware Reset function, which is executed whenever the RESET

¯¯¯¯¯¯ input is asserted (logic 0). The

RESET

¯¯¯¯¯¯ input is active low and is referenced to the DBVDD1 power domain.

A Hardware Reset causes almost all of the CS47L85 control registers to be reset to their default states. The only exception

is the contents of the DSP6 firmware memory, which are retained during Hardware Reset, provided DCVDD is held above

its reset threshold.

An internal pull-up resistor is enabled by default on the RESET

¯¯¯¯¯¯ pin; this can be configured using the RESET_PU register bit.

A pull-down resistor is also available, as described in Table 134. When the pull-up and pull-down resistors are both enabled,

the CS47L85

provides a ‘bus keeper’ function on the RESET

¯¯¯¯¯¯ pin. The bus keeper function holds the input logic level

unchanged whenever the external circuit removes the drive (e.g., if the signal is tri-stated).

If the CS47L85 SLIMbus component is in its operational state, then it must be reset prior to scheduling a Hardware Reset.

See

“SLIMbus Interface Control” for details of the SLIMbus reset control messages.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6864

(1AD0h)

AOD_Pad

_Ctrl

RESET_PU

RESET Pull-up enable

0 = Disabled

1 = Enabled

Note - when RESET_PD and RESET_PU

are both set to ‘1’, then a ‘bus keeper’

function is enabled on the RESET pin.

RESET_PD

RESET Pull-down enable

0 = Disabled

1 = Enabled

Note - when RESET_PD and RESET_PU

are both set to ‘1’, then a ‘bus keeper’

function is enabled on the RESET pin.

Table 134 Reset Pull-Up Configuration

A Software Reset is executed by writing any value to register R0. A Software Reset causes most of the CS47L85 control

registers to be reset to their default states. Note that the Control Write Sequencer memory and the firmware memory contents

of DSP6 are retained during Software Reset.

Note that the first register read/write operation following a Software Reset may be unsuccessful, if the register access is

attempted via a different Control Interface to the one that commanded the Software Reset. Note that only the first register

read/write is affected, and only when using more than one Control Interface.

A Wake-Up transition (from Sleep mode) is similar to a Software Reset, but selected functions and control registers are

maintained via an ‘Always-On’ internal supply domain. The ‘Always-On’ registers are not reset during Wake-Up. See “Low

Power Sleep Configuration

” for details of the ‘Always-On’ functions.

The Control Write Sequencer memory contents will revert to its default contents following Power-On Reset (POR), Hardware

Reset, or a Sleep mode transition. The control sequences (including any user-defined sequences) are maintained in the

sequencer memory through Software Reset.

The DSP firmware memory contents are cleared following Power-On Reset (POR), or a Sleep mode transition. The firmware

memory contents are not affected by Software Reset, provided DCVDD is held above its reset threshold. On DSP1 to DSP5,

and on DSP7, the firmware memory contents are cleared under Hardware Reset conditions. On DSP6 only, the firmware

memory is retained through Hardware Reset, provided DCVDD is held above its reset threshold.

See the “Applications Information” section for a summary of the CS47L85 memory reset conditions. The DSPn_MEM_ENA

If DCVDD is powered from LDO1, it is recommended that the LDOENA pin is asserted (logic 1) before Hardware Reset or

Software Reset; this ensures the DSP memory contents can be retained, and also allows faster reset time.

Following Hardware Reset, Software Reset or Wake-Up (from Sleep mode), a Boot Sequence is executed. The

BOOT_DONE_STSx register (see Table 132) is de-asserted during Hardware Reset, Software Reset and in Sleep mode.

The BOOT_DONE_STSx register is asserted on completion of the Boot Sequence. Control register writes should not be

attempted until BOOT_DONE_STSx has been asserted.

The BOOT_DONE_STSx status is an input to the Interrupt control circuit and can be used to trigger an Interrupt event - see

“Interrupts”.

CS47L85 Datasheet(PDF) 346 Page - Cirrus Logic

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