CS47L85 datasheet(343/370 Pages) CIRRUS

343 / 370 page

CS47L85

Rev 4.3

343

POWER-ON RESET (POR)

The CS47L85 will remain in the reset state until AVDD, DBVDD1 and DCVDD are all above their respective reset thresholds.

Note that specified device performance is not assured outside the voltage ranges defined in the “Recommended Operating

Conditions

” section.

Refer to “Recommended Operating Conditions” for the CS47L85 power-up sequencing requirements.

If DCVDD is powered from LDO1, then the DCVDD supply must be enabled using the LDOENA pin for the initial power-up.

Note that subsequent interruption to DCVDD should only be permitted as part of a control sequence for entering Sleep mode.

After the initial power-up, the Power-On Reset will be re-scheduled following an interruption to the DBVDD1 or AVDD

supplies.

If the CS47L85 SLIMbus component is in its operational state, then it must be reset prior to scheduling a Power-On Reset.

See “SLIMbus Interface Control” for details of the SLIMbus reset control messages.

Following Power-On Reset (POR), a Boot Sequence is executed. The BOOT_DONE_STSx register is asserted on

completion of the Boot Sequence, as described in Table 132. Control register writes should not be attempted until

BOOT_DONE_STSx has been asserted.

The BOOT_DONE_STS signal is an input to the Interrupt control circuit and can be used to trigger an Interrupt event on

completion of the Boot Sequence - s

ee “Interrupts”. Under default register conditions, a falling edge on the IRQ

¯¯¯ pin will

indicate completion of the Boot Sequence.

For details of the Boot Sequence

, see “Control Write Sequencer”.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R6272

(1880h)

IRQ1_Ra

w_Status_

BOOT_DONE_S

TS1

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be

attempted until Boot Sequence has

completed.

R6528

(1980h)

IRQ2_Ra

w_Status_

BOOT_DONE_S

TS2

Boot Status

0 = Busy (boot sequence in progress)

1 = Idle (boot sequence completed)

Control register writes should not be

attempted until Boot Sequence has

completed.

Table 132 Device Boot-Up Status

The CS47L85 is in Sleep mode when AVDD and DBVDD1 are present, and DCVDD is below its reset threshold. (Note that

specific control requirements are also applicable for entering Sleep mode, as described in “Low Power Sleep Configuration”.)

In Sleep mode, most of the Digital Core (and control registers) are held in reset; selected functions and control registers are

maintained via an ‘Always-On’ internal supply domain. See “Low Power Sleep Configuration” for details of the ‘Always-On’

functions.

See “Hardware Reset, Software Reset, Wake-Up, and Device ID” for details of the Wake-Up transition (exit from Sleep

mode).

Table 133 describes the default status of the CS47L85 digital I/O pins on completion of Power-On Reset, prior to any register

writes. The same default conditions are also applicable on completion of a Hardware Reset or Software Reset (see

“Hardware Reset, Software Reset, Wake-Up, and Device ID”).

The same default conditions are applicable following a Wake-Up transition, except for the IRQ

¯¯¯, LDOENA and RESET

¯¯¯¯¯¯ pins.

These are ‘Always-On’ pins whose configuration is unchanged in Sleep mode and during a Wake-Up transition.

Note that the default conditions described in Table 133

will not be valid if modified by the Boot Sequence or by a ‘Wake-Up’

control sequence.

See “Control Write Sequencer” for details of these functions.

CS47L85 Datasheet(PDF) 343 Page - Cirrus Logic

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