CS47L85 datasheet(336/370 Pages) CIRRUS

336 / 370 page

CS47L85

336

Rev 4.3

from the MICVDD pin, and use the internal bandgap circuit as a reference.

In Regulator mode, the MICBIAS regulators are designed to operate without external decoupling capacitors. The regulators

can be configured to support a capacitive load if required, using the MICBn_EXT_CAP register bits. (This may be appropriate

for a digital microphone supply.) It is important that the external capacitance is compatible with the applicable

MICBn

_EXT_CAP setting. The compatible load conditions are detailed in the “Electrical Characteristics” section.

In Bypass mode (MICBn_BYPASS=1), the output pin (MICBIASn) is connected directly to MICVDD. This enables a low

power operating state. Note that the MICBn_EXT_CAP register settings are not applicable in Bypass mode; there are no

restrictions on the external MICBIAS capacitance in Bypass mode.

The MICBIAS generators incorporate a pop-free control circuit to ensure smooth transitions when the MICBIAS outputs are

enabled or disabled in Bypass mode; this feature is enabled using the MICBn_RATE registers.

The MICBIAS generators are illustrated in Figure 86. The MICBIAS control register bits are descrbed in Table 129.

The maximum output current for each MICBIASn

pin is noted in the “Electrical Characteristics”. This limit must be observed

on each MICBIAS output, especially if more than one microphone is connected to a single MICBIAS pin. Note that the

maximum output current differs between Regulator mode and Bypass mode.

VOLTAGE REFERENCE CIRCUIT

The CS47L85 incorporates a voltage reference circuit, powered by AVDD. This circuit ensures the accuracy of the LDO

Regulator and MICBIAS voltage settings.

LDO1 REGULATOR AND DCVDD SUPPLY

The LDO1 voltage regulator is powered by LDOVDD, and is intended for generating the DCVDD domain, which powers the

digital core functions on the CS47L85. In this configuration, the LDO output (LDOVOUT) should be connected to the DCVDD

pin. Note that the use of the LDO1 regulator to power external circuits cannot be supported by the CS47L85.

LDO1 is enabled when a

logic ‘1’ is applied to the LDOENA pin. The logic level is determined with respect to the DBVDD1

voltage domain.

When LDO1 is disabled, the LDOVOUT pin can be configured to be floating or to be actively discharged. This is selected

using the LDO1_DISCH register bit.

It is possible to supply DCVDD from an external supply. In this configuration, the LDOVOUT pin should be left floating: it

must not be connected to the DCVDD pin. The LDO1 regulator is not used in this case, and must be disabled at all times.

An internal pull-down resistor is enabled by default on the LDOENA pin. This is configurable using the LDO1ENA_PD register

bit. A pull-up resistor is also available, as described in Table 129. When the pull-up and pull-down resistors are both enabled,

the CS47L85

provides a ‘bus keeper’ function on the LDOENA pin. The bus keeper function holds the input logic level

unchanged whenever the external circuit removes the drive (e.g., if the signal is tri-stated).

If DCVDD is powered from LDO1, then a logic ‘1’ must be applied to the LDOENA pin during power-up, to enable LDO1.

The LDO must also be enabled using the LDOENA pin following a Hardware Reset or Software Reset, to allow the device

to re-

start. (It is recommended that the LDOENA pin is asserted before any reset, and is held at logic ‘1’ until after the reset

is complete; this ensures the DSP6 firmware memory contents can be retained, and also allows faster reset time.)

For normal operation following Power-On Reset (POR), Hardware Reset, or Software Reset, LDO1 must be enabled using

the LDOENA pin. The ‘bus keeper’ function can be used during normal operation to keep LDO1 enabled without actively

driving the LDOENA pin. Note that the LDOENA pin must always be actively driven following a reset, as the bus keeper

function will be disabled in this case.

See “Power-On Reset (POR)” and “Hardware Reset, Software Reset, Wake-Up, and Device ID” for details of CS47L85

Resets. See also “Low Power Sleep Configuration” for details of the Sleep / Wake-up functions.

The LDO1 Regulator circuit is illustrated in Figure 86. The associated register control bits are described in Table 129.

Note that the LDO output requires an external decoupling capacitor; this requirement is typically achieved via decoupling on

the DCVDD pins. Refer to the

“Applications Information” section for recommended external components.

CS47L85 Datasheet(PDF) 336 Page - Cirrus Logic

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