CS47L85 datasheet(334/370 Pages) CIRRUS

334 / 370 page

CS47L85

334

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

7:0

WSEQ_DATA0

[7:0]

00h

Data to be written in this sequence

step. When the data width is less

than 8 bits, then one or more of the

MSBs of WSEQ_DATAn are ignored.

It is recommended that unused bits

be set to 0.

Table 126 Write Sequencer Control - Programming a Sequence

SEQUENCER MEMORY DEFINITION

The Write Sequencer memory defines up to 508 write operations; these are indexed as 0 to 507 in the sequencer memory

map.

The Write Sequencer memory will revert to its default contents following Power-On Reset (POR), Hardware Reset, or a

Sleep mode transition, In these cases, the sequence memory will contain the Boot Sequence, and the OUT1, OUT2, OUT3,

OUT4 signal path enable/disable sequences; the remainder of the sequence memory will be undefined.

User-defined sequences can be programmed after power-up. The user-defined control sequences must be reconfigured by

the host processor following Power-On Reset (POR), Hardware Reset, or following a Sleep mode transition. Note that all

control sequences are maintained in the sequencer memory through Software Reset. See the “Applications Information”

section for a summary of the CS47L85 memory reset conditions.

The default control sequences can be overwritten in the sequencer memory, if required. Note that the headphone and

earpiece output path enable registers (HPnx_ENA, SPKOUTx_ENA) will always trigger the Write Sequencer (at the pre-

determined start index addresses).

Writing ‘1’ to the WSEQ_LOAD_MEM bit will clear the sequencer memory to the POR state.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (0018h)

Write_Sequen

cer_Ctrl_2

WSEQ_LOAD_

MEM

Writing a 1 to this bit resets the

sequencer memory to the POR state.

Table 127 Write Sequencer Control - Load Memory Control

The sequencer memory is summarised in Table 128. User-defined sequences should be assigned space within the allocated

portion (‘user space’) of the Write Sequencer memory.

The start index for the user-defined sequences is configured using the registers described in Table 119 through to Table

123.

DESCRIPTION

SEQUENCE INDEX RANGE

Default Sequences

0 to 302

User Space

303 to 383

Boot Sequence

384 to 507

Table 128 Write Sequencer Memory Allocation

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