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MEC1632 Datasheet(PDF) 57 Page - Microchip Technology

Part # MEC1632
Description  Low Power 32-Bit Mobile Embedded Controller
PDF  636 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MEC1632 Datasheet(HTML) 57 Page - Microchip Technology

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 2012-2018 Microchip Technology Inc.
DS00001592B-page 57
MEC1632
4.3
Address Space
The ARC EC has a 24-bit address space. Addresses in the lower half of the range, 0h through 7F_FFFFh, can be used
for both instruction access and data access. The address range 0h through 4_FFFFh (which includes the 192KB Flash
Memory Array is mapped to the Embedded Flash Subsystem. The address range 10_0000h through 10_0FFFh is
mapped to the Boot ROM. Addresses in the range 80_0000h through 80_3FFFh are mapped to the Closely Coupled
Data Memory. These memories are shown in Figure 4-2. Software can change the address mapping so that the Closely
Coupled Data Memory is mapped to 6_0000h through 6_0FFFh, where it can be used for both instructions and data,
and the Embedded Flash becomes accessible only through a register interface. Addresses greater or equal to
80_1000h are propagated through the AHB interface on the ARC processor. References, by either the EC or the Host
via the LPC bus, to addresses that are not mapped to any device register or memory will cause a bus error; see Section
4.4.3, "AHB Bus Errors," on page 62.
4.3.1
ARC ADDRESS SPACE
The ARC Address Space is illustrated in Figure 4-2, "MEC1632 EC Memory Map" & Figure 4-1, "MEC1632 Bus Hier-
archy". EC Instruction Memory occupies the lower half of the address space, 00_0000h through 7F_FFFFh. The ARC
processor can only execute instructions that are located in the Instruction Memory portion of the address space. Only
a portion of the Instruction space is populated.
The upper half of the address space is used solely for data references. The region contains a general-purpose EC Data
Memory SRAM as well as the address space of the two SPB peripheral buses.
The contents of the Instruction memory can be read and written by the ARC processor through regular load and store
instructions. However, there may be a one cycle instruction fetch penalty whenever a data load or store instruction to
Instruction memory is executed.



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