MEC1632 datasheet(96/636 Pages) MICROCHIP

96 / 636 page

MEC1632

DS00001592B-page 96

 2012-2018 Microchip Technology Inc.

7.3

Port List

TABLE 7-4:

Power, Clocks, and Resets Port List

Signal Name

Direction

Source

Destination

Description

ARC_CLK_DIS-

ABLE

Input

External -

Embedded

Controller Core

(EC)

Internal - EC

Power State Con-

trols

Indication for the Power Management

Interface (see Section 7.4.10 on

page 111) that an EC Sleep instruction

has occurred and the processor is

sleeping or halted.

SLEEP_STATE

Output

Internal - EC

Power State

Controls

Internal - 20 MHz

Oscillator Control

and External

Functions as

Needed.

System Sleeping State status indicator

as described in "EC Power State Con-

trols," on page 115.

SLEEP_FLAG

Output

Clock Control

Internal - 20 MHz

Oscillator Con-

trol, Block Sleep

Enables and

External Func-

tions as Needed.

Sleep indicator from the Clock Control

Controls," on page 115 and "Block Sleep

Enables," on page 117.

PCI_CLK

Input

External

Internal Test

Functions

33 MHz PCI Clock Input (also TEST_-

CLK_IN).

LRESET#

Input

External

Internal

PCI Reset. See Section 7.7.3, "LPC

RESET," on page 129.

WAKE

Input

External

Internal - Wake

Interface

Aggregated Wake indicator from the

Section 17.0, "EC Interrupt Aggregator,"

on page 287 for the Power Management

Interface (see Section 7.4.10 on

page 111).

WDT_ALRT

Input

External

Internal - Reset

Interface

Causes a Watch-Dog Timer Forced

Reset as described in Section 7.7.4,

"Watch-Dog Timer Forced Reset," on

page 130.

ALL BLOCK

SLEEP ENABLE

OUTPUTS

Output

Internal - Block

Sleep Enables

External - Sleep-

able Blocks

To all blocks as defined in Section 7.8.4,

"Block Sleep Enable Registers," on

page 136. See also "Block Sleep

Enables," on page 117

MCLK,

EC_BUS_CLK_EN,

LPC_BUS_CLK_EN,

MCLK_DIV1_EN,

MCLK_DIV2_EN,

MCLK_DIV4_EN,

MCLK_DIV8_EN,

MCLK_DIV10_EN,

MCLK_DIV16_EN,

MCLK_DIV20_EN,

MCLK_DIV32_EN,

MCLK_DIV64_EN,

MCLK_DIV128_EN,

MCLK_DIV203_EN,

MCLK_5HZ_EN,

MCLK_DIV20_EN_HST,

X32K_CLK

Output

Internal - MCLK

Sourced Clock-

ing and 32K

Clock Domain

External

See Section 7.4.11, "MCLK Sourced

Clocking," on page 120 and Section

7.4.12, "32K Clock Domain," on

page 121.

XTAL1

Input

External

Internal - 32.768

KHz Crystal

Oscillator

32.768 KHz Crystal Oscillator

crystal input pin.

XTAL2

Output

External

Internal - 32.768

KHz Crystal

Oscillator

32.768 KHz Crystal Oscillator

crystal output pin.

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