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MEC1632 Datasheet(PDF) 89 Page - Microchip Technology

Part # MEC1632
Description  Low Power 32-Bit Mobile Embedded Controller
PDF  636 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MEC1632 Datasheet(HTML) 89 Page - Microchip Technology

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 2012-2018 Microchip Technology Inc.
DS00001592B-page 89
MEC1632
6.9
LPC Logical Device Configuration Registers
The configuration registers in the LPC Logical Device are described in Section 5.0, "Logical Device Configuration," on
page 63. These registers control the activity of all the Logical Devices in the MEC1632. The Activate Register controls
the LPC device itself. The Host can shut down the LPC Logical Device by clearing the Activate bit, but it cannot restart
the LPC interface, since once the LPC interface is inactive the Host has no access to any registers on the MEC1632.
The Embedded Controller can set or clear the Activate bit at any time.
ACTIVATE
When this bit is 1, the LPC Logical Device is powered and functional.
When this bit is 0, the logical device is powered down and inactive. Except for the Activate Register itself, clocks to the
block are gated and the LPC Logical Device will permit the ring oscillator to be shut down (see Section 6.10.4, "EC Clock
Control Register," on page 92). LPC bus output pads will be tri-stated. Serial IRQ activation is separately controlled by
the Device Mode register in the Chip-Level (Global) Control/Configuration Registers.
APPLICATION NOTE:
The Activate bit in the Activate Register should not be written ‘0’ to by the Host over LPC.
6.10
LPC Logical Device EC-only Registers
Table 6-7, "LPC EC-only Registers" summarizes the registers in the Host Interface block that are only accessible by the
EC. In addition to these registers, the Host Interface also contains Configuration registers, described in Section 5.0,
"Logical Device Configuration," on page 63.
Because their addresses are in the part of the LPC Logical Device address frame that is not addressable from the LPC
bus, the following registers are accessible only to the EC.
TABLE 6-6:
ACTIVATE REGISTER
HOST OFFSET
BYTE0: 30h
8-bit HOST SIZE
EC ADDRESS
FF_3330h
8-bit EC SIZE
POWER
VTR
00b nSYS_RST DEFAULT
BUS
LPC SPB
BYTE0 BIT
D7
D6D5
D4D3D2
D1
D0
HOST TYPE
R
RRRRR
R
R/W
EC TYPE
R
RRRRR
R
R/W
BIT NAME
Reserved
Activate
TABLE 6-7:
LPC EC-ONLY REGISTERS
AHB Address
Name
VTR POR (
nSYS_RST) Default
FF_3100h
Reserved
0000_0000h
FF_3104h
LPC Bus Monitor Register
0000_0000h
FF_3108h
Host Bus Error Register
0000_0000h
FF_310Ch
EC SERIRQ Register
0000_0000h
FF_3110h
EC Clock Control Register
0000_0000h
FF_3120h
BAR Inhibit Register
0000_0000_0000_0000h
FF_3130h
BAR Init Register
0000_002Eh
FF_3140h
Mem BAR Inhibit Register
0000_0000_0000_0000h



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