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MEC1632 Datasheet(PDF) 60 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 60 Page - Microchip Technology |
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60 / 636 page ![]() MEC1632 DS00001592B-page 60 2012-2018 Microchip Technology Inc. Note 4-1 All VBAT powered registers are in a Single 1KB Frame separated by 128 bytes (see Table 4-3, Logical Device Number 33h.) Note that the ARC-only SPB Bridge address space uses the terminology of Logical Device; however, there is no host access to these blocks. Note 4-2 PWM register addressing within Logical device 17h, PWM(15-8), is similar to the addressing within the PWM(7-0) logical address space. TABLE 4-3: EC LOGICAL DEVICES ON MEC1632 Logical Device Number AHB Address for Base of Frame Logical Devices Notes 0h F0_0000h Hibernation Timer 1h F0_0400h Watchdog Timer 2h F0_0800h Input Capture and Compare Timer 3h F0_0C00h 16-bit Timer 4h F0_1000h RC ID 5h F0_1400h BC Bus Master 6h F0_1800h SMBus 7h F0_1C00h EC GP-SPI 8h F0_2000h Keyscan Interface 9h F0_2400h DMA Ah F0_2800h SPI Flash Read Bh F0_2C00h EEPROM Ch - Fh F0_3000h - F0_3FFFh Reserved 10h F0_4000h CEC Interface Controller 11h F0_4400h Reserved 12h F0_4800h Reserved 14h - 15h F0_5000h - F0_57FFh Reserved 16h F0_5800h PWM(7-0) 17h F0_5C00h PWM(15-8) Note 4-2 18h F0_6000h TACH 19h F0_6400h PECI 1Ah F0_6800h ADC 1Bh - 20h F0_6C00h - F0_83FFh Reserved 21h F0_8400h LED 22h F0_8800h PS/2 23h F0_8C00h MCU Debug Port 24h - 2Fh F0_9000h - F0_BCFFh Reserved 30h F0_C000h EC Interrupt Aggregator 31h F0_C400h GPIOs 32h F0_C800h Power, Clock & Reset (VTR PWR’ed) 33h F0_CC00h Power, Clock & Reset (VBAT PWR’ed) F0_CC80h Week Alarm Timer F0_CD00h VBAT Backed Memory 34h F0_D000h VBAT-Powered Control Interface 35h - 3Dh F0_D400h - F0_F7FFh Reserved 3Eh F0_F800h Reserved 3Fh F0_FC00h System Registers |
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