MEC1632 datasheet(66/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 66

 2012-2018 Microchip Technology Inc.

5.5.3

CONFIGURATION SEQUENCE EXAMPLE

To program the configuration registers, the following sequence must be followed:

Enter Configuration State

Program the Configuration Registers

Exit Configuration State.

The following is an example of a configuration program in Intel 8086 assembly language.

;----------------------------.

; ENTER CONFIGURATION STATE

;----------------------------'

MOV DX,CONFIG_PORT_BASE_ADDRESS

MOV AX,055H ; Config Entry Key

OUT DX,AL

;----------------------------.

; CONFIGURE BASE ADDRESS,

; LOGICAL DEVICE 8

;----------------------------'

MOV DX,CONFIG_PORT_BASE_ADDRESS

MOV AL,07H

OUT DX,AL ; Point to LD# Config Reg

MOV DX,CONFIG_PORT_BASE_ADDRESS+1

MOV AL, 08H

OUT DX,AL ; Point to Logical Device 8

;

MOV DX,CONFIG_PORT_BASE_ADDRESS

MOV AL,60H

OUT DX,AL ; Point to BASE ADDRESS REGISTER

MOV DX,CONFIG_PORT_BASE_ADDRESS+1

MOV AL,02H

OUT DX,AL ; Update BASE ADDRESS REGISTER

;-----------------------------.

; EXIT CONFIGURATION STATE

;-----------------------------'

MOV DX,CONFIG_PORT_BASE_ADDRESS

MOV AX,0AAH ; Config Exit Key

OUT DX,AL.

5.5.4

CONFIGURATION REGISTER ADDRESS MAPPING

The INDEX PORT defines 256 bytes for configuration. The first 48 of these bytes are Global Configuration registers,

which reside in the first 48 bytes of the Configuration part of the address frame for Logical Device 3Fh. Values of INDEX

greater than 48 map into registers that are specific to the Logical Device specified in the Global Configuration Logical

Device Number Register 7h. These registers reside in upper 20 bytes of the Logical Device address frame. See Section

5.9.2, on page 74 for details.

5.6

Configuring Runtime Register Addresses

5.6.1

RUNTIME REGISTERS

Runtime Registers are registers that are accessible to the Host within the Host I/O address space. These Host I/O

accesses are all mapped into the MEC1632 AHB address space onto devices located on the LPC SPB. Runtime reg-

isters all reside within the first 256 bytes of a 1KB Logical Device address frame. The Host accesses these registers

with 8-bit LPC I/O accesses. Each 8-bit I/O address is mapped into an 8-bit address in the AHB address space, so the

first 256 bytes of the Logical Device frame can accommodate 256 LPC Runtime Registers per Logical Device. The Host

I/O addresses are determined by a block of Base Address Registers located in the LPC Logical Device. The Embedded

Controller can access all the Runtime Registers as well, using loads and stores to full AHB addresses.

5.6.2

BASE ADDRESS REGISTERS

Each Logical Device has a Base Address Register (BAR). These BARs are located in blocks of Configuration Registers

in Logical Device 0Ch, in the AHB address range FF_3360h through FF_3384h. On every LPC bus I/O access all Base

Address Registers are checked in parallel and if any matches the LPC I/O address the MEC1632 claims the bus cycle.

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