LM5145 datasheet(55/70 Pages) TI

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components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then

include snubber components as needed.

9.4.1.2 Gate-Drive Layout

The LM25148-Q1 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time

control, and low-impedance output stages capable of delivering large peak currents with very fast rise and

fall times to facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause

unacceptable ringing if the trace lengths and impedances are not well controlled.

Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,

whether it be series gate inductance that resonates with MOSFET gate capacitance or common source

inductance (common to gate and power loops) that provides a negative feedback component opposing the

gate drive command, thereby increasing MOSFET switching times. The following loops are important:

• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap

(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot

capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from

the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side

MOSFET through the SW trace. Refer to loop 2 of Figure 9-46.

• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turnon, high current flows from the VCC

decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the

capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of

the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET

through ground. Refer to loop 3 of Figure 9-46.

TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive

circuits.

• Connections from gate driver outputs, HO and LO, to the respective gates of the high-side or low-side

MOSFETs must be as short as possible to reduce series parasitic inductance. Be aware that peak gate drive

currents can be as high as 3.3 A. Use 0.65 mm (25 mils) or wider traces. Use via or vias, if necessary, of at

least 0.5 mm (20 mils) diameter along these traces. Route HO and SW gate traces as a differential pair from

the LM5148 to the high-side MOSFET, taking advantage of flux cancellation.

• Minimize the current loop path from the VCC and HB pins through their respective capacitors as these

provide the high instantaneous current, up to 3.3 A, to charge the MOSFET gate capacitances. Specifically,

locate the bootstrap capacitor, CBST, close to the CBOOT and SW pins of the LM25148-Q1 to minimize the

area of loop 2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the

VCC and PGND pins of the LM5148 to minimize the area of loop 3 associated with the low-side driver.

9.4.1.3 PWM Controller Layout

With the proviso to locate the controller as close as possible to the power MOSFETs to minimize gate driver

trace runs, the components related to the analog and feedback signals as well as current sensing are considered

in the following:

• Separate power and signal traces, and use a ground plane to provide noise shielding.

• Place all sensitive analog traces and components related to COMP, FB, ISNS+, and RT away from high-

voltage switching nodes such as SW, HO, LO, or CBOOT to avoid mutual coupling. Use internal layer or

layers as ground plane or planes. Pay particular attention to shielding the feedback (FB) and current sense

(ISNS+ and VOUT) traces from power traces and components.

• Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short

as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at

the load.

• Route the ISNS+ and VOUT sense traces as differential pairs to minimize noise pickup and use Kelvin

connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor (if

inductor DCR current sensing is used).

• Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the

PGND pin. Locate these capacitors as close as possible to the LM5148.

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LM5148

SNVSC01 – FEBRUARY 2023

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