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AFE7901 Datasheet(PDF) 6 Page - Texas Instruments |
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AFE7901 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 160 page  Table 6-1. Pin Functions (continued) BALL NAME BALL NUMBER TYPE(1) DESCRIPTION 7SRX– V1 I CML SerDes Interface Lane 7 input: negative terminal 7SRX+ W1 I CML SerDes Interface Lane 7 input: positive terminal. Unused Serdes inputs can be left open. 8SRX– Y2 I CML SerDes Interface Lane 8 input: negative terminal 8SRX+ Y3 I CML SerDes Interface Lane 8 input: positive terminal. Unused Serdes inputs can be left open. 1STX– C3 O CML SerDes Interface Lane 1 output: negative terminal. Unused Serdes outputs can be left open. 1STX+ C4 O CML SerDes Interface Lane 1 output: positive terminal. Unused Serdes outputs can be left open. 2STX– E3 O CML SerDes Interface Lane 2 output: negative terminal. Unused Serdes outputs can be left open. 2STX+ E4 O CML SerDes Interface Lane 2 output: positive terminal. Unused Serdes outputs can be left open. 3STX– G4 O CML SerDes Interface Lane 3 output: negative terminal. Unused Serdes outputs can be left open. 3STX+ G3 O CML SerDes Interface Lane 3 output: positive terminal. Unused Serdes outputs can be left open. 4STX– J4 O CML SerDes Interface Lane 4 output: negative terminal. Unused Serdes outputs can be left open. 4STX+ J3 O CML SerDes Interface Lane 4 output: positive terminal. Unused Serdes outputs can be left open. 5STX– M4 O CML SerDes Interface Lane 5 output: negative terminal. Unused Serdes outputs can be left open. 5STX+ M3 O CML SerDes Interface Lane 5 output: positive terminal. Unused Serdes outputs can be left open. 6STX– P4 O CML SerDes Interface Lane 6 output: negative terminal. Unused Serdes outputs can be left open. 6STX+ P3 O CML SerDes Interface Lane 6 output: positive terminal. Unused Serdes outputs can be left open. 7STX– T3 O CML SerDes Interface Lane 7 output: negative terminal. Unused Serdes outputs can be left open. 7STX+ T4 O CML SerDes Interface Lane 7 output: positive terminal. Unused Serdes outputs can be left open. 8STX– V3 O CML SerDes Interface Lane 8 output: negative terminal. Unused Serdes outputs can be left open. 8STX+ V4 O CML SerDes Interface Lane 8 output: positive terminal. Unused Serdes outputs can be left open. GPIO FUNCTIONS GBL_0_GPIO13 V6 I/O GPIO. GBL_1_FBTDD2 R6 I/O Default location of FB TDD2 input signal. GBL_2_FSPICLKC U5 I/O Default and recommended location of FSPI C clock (FSPI for factory use only, available as generic GPIO). GBL_3_GPIO14 R5 I/O GPIO. GBL_4_RXDLNB T5 I/O Default location of RX channel D AGC LNA Bypass output signal. GBL_5_GPIO15 N10 I/O GPIO. GBL_6_GPIO16 P10 I/O GPIO. AFE7901 SBASAO5 – APRIL 2023 www.ti.com 6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE7901 |
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