AFE7901 datasheet(91/160 Pages) TI

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7.12.9 TX Typical Characteristics at 800 MHz (continued)

Typical values at TA = +25°C with nominal supplies. Unless otherwise noted, TX input data rate = 491.52 MSPS, fDAC =

11796.48 MSPS, interleave mode, AOUT = –1 dBFS, 1st Nyquist zone output, Internal PLL, fREF = 491.52 MSPS, 24x

Interpolation, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled

Temperature (Cq)

-40

-15

105

2.5

3.5

4.5

5.5

6.5

fdac=5898.24MSPS, straight mode

fdac=5898.24MSPS, interleaved mode

fdac=8847.36MSPS, straight mode

fdac=8847.36MSPS, interleaved mode

fdac=11796.48MSPS, interleaved mode

including PCB and cable losses, Aout = -0.5 dFBS, DSA = 0,

0.8 GHz matching

Figure 7-309. TX Output Fullscale vs Temperature

DSA (dB)

-35

-30

-25

-20

-15

-10

-5

1TX

2TX

3TX

4TX

fDAC = 11796.48 MSPS, interleave mode, Aout = -0.5 dFBS,

matching 0.8 GHz

Figure 7-310. TX Output Power vs DSA Setting and Channel at

0.85 GHz

DSA (dB)

-0.05

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

0.05

1TX

2TX

3TX

4TX

fDAC=5898.24 MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA

Setting) + 1

Figure 7-311. TX Uncalibrated Differential Gain Error vs DSA

Setting and Channel at 0.85 GHz

DSA (dB)

-0.05

-0.04

-0.03

-0.02

-0.01

0.01

0.02

0.03

0.04

0.05

1TX

2TX

3TX

4TX

fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz

Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA

Setting) + 1

Figure 7-312. TX Calibrated Differential Gain Error vs DSA

Setting and Channel at 0.85 GHz

DSA (dB)

0.05

0.1

0.15

0.2

0.25

0.3

0.35

1TX

2TX

3TX

4TX

fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA

Setting = 0) + DSA Settings

Figure 7-313. TX Uncalibrated Integrated Gain Error vs DSA

Setting and Channel at 0.85 GHz

DSA (dB)

-0.02

0.02

0.04

0.06

0.08

0.1

1TX

2TX

3TX

4TX

fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz

Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA

Setting = 0) + DSA Setting

Figure 7-314. TX Calibrated Integrated Gain Error vs DSA

Setting and Channel at 0.85 GHz

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AFE7901

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