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AFE7901 Datasheet(PDF) 92 Page - Texas Instruments |
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AFE7901 Datasheet(HTML) 92 Page - Texas Instruments |
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92 / 160 page  7.12.9 TX Typical Characteristics at 800 MHz (continued) Typical values at TA = +25°C with nominal supplies. Unless otherwise noted, TX input data rate = 491.52 MSPS, fDAC = 11796.48 MSPS, interleave mode, AOUT = –1 dBFS, 1st Nyquist zone output, Internal PLL, fREF = 491.52 MSPS, 24x Interpolation, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX Clock Dither Enabled DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 -40 qC 25 qC 105 qC fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 7-315. TX Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 0.85 GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 -40 qC 25 qC 105 qC fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Differential Gain Error = POUT(DSA Setting – 1) – POUT(DSA Setting) + 1 Figure 7-316. TX Calibrated Differential Gain Error vs DSA Setting and Temperature at 0.85 GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40 qC 25 qC 105 qC fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting Figure 7-317. TX Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85 GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 -40 qC 25 qC 105 qC fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Integrated Gain Error = POUT(DSA Setting ) – POUT(DSA Setting = 0) + DSA Setting Figure 7-318. TX Calibrated Integrated Gain Error vs DSA Setting and Temperature at 0.85 GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.02 -0.01 0 0.01 0.02 1TX 2TX 3TX 4TX fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Figure 7-319. TX Uncalibrated Differential Phase Error vs DSA Setting and Channel at 0.85 GHz DSA (dB) 0 4 8 12 16 20 24 28 32 36 40 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 1TX 2TX 3TX 4TX fDAC = 5898.24 MSPS, interleave mode, matching at 0.8 GHz Differential Phase Error = PhaseOUT(DSA Setting – 1) – PhaseOUT(DSA Setting) Phase DNL spike may occur at any DSA setting. Figure 7-320. TX Calibrated Differential Phase Error vs DSA Setting and Channel at 0.85 GHz AFE7901 SBASAO5 – APRIL 2023 www.ti.com 92 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AFE7901 |
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