LXT9785 datasheet(80/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

3.4

BGA23 Signal Descriptions

3.4.1

Signal Name Conventions

Signal names may contain either a port designation or a serial designation, or a combination of the

two designations. Signal naming conventions are as follows:

• Port Number Only. Individual signals that apply to a particular port are designated by the

Signal Mnemonic, immediately followed by the Port Designation. For example, Transmit

Enable signals would be identified as TxEN0, TxEN1, and TxEN2.

• Serial Number Only. A set of signals which are not tied to any specific port are designated by

the Signal Mnemonic, followed by an underscore and a serial designation. For example, a set

of three Global Configuration signals would be identified as CFG_1, CFG_2, and CFG_3.

• Port and Serial Number. In cases where each port is assigned a set of multiple signals, each

signal is designated in the following order: Signal Mnemonic, Port Designation, an

underscore, and the serial designation. For example, a set of three Port Configuration signals

would be identified as RxData0_0 and RxData0_1, RxData1_0 and RxData1_1, and

RxData2_0 and RxData2_1.

3.4.2

Signal Descriptions – RMII, SMII, and SS-SMII Configurations

Table 24. Intel® LXT9785/LXT9785E RMII Signal Descriptions – BGA23 (Sheet 1 of 3)

Ball/Pin

Designation

Symbol

Type1

Signal Description2,3

BGA23

PQFP

E6,

E12

REFCLK0

REFCLK1

Reference Clock.

50 MHz RMII reference clock is always required. RMII

inputs are sampled on the rising edge of REFCLK,

RMII outputs are sourced on the falling edge. See

“Clock/SYNC Requirements” on page 125. for detailed

CLK requirements.

E2,

TxData0_0

TxData0_1

I, ID

Transmit Data - Port 0.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 0 are clocked in synchronously to REFCLK.

C3,

TxData1_0

TxData1_1

I, ID

Transmit Data - Port 1.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 1 are clocked in synchronously to REFCLK

TxData2_0

TxData2_1

I, ID

Transmit Data - Port 2.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 2 are clocked in synchronously to REFCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

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