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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Table 10. Intel® LXT9785/LXT9785E Signal Detect – PQFP

Pin/Ball

Designation

Symbol

Type1

Signal Description2,3

PQFP

PBGA

SD_2P5V

I, ST, ID

Signal Detect 2.5 Volt Interface.

SD input threshold voltage select.

Tie to VCCPECL = Select 2.5 V LVPECL input levels

Float or Tie to GNDPECL = Select 3.3 V LVPECL input

levels

100

101

161

162

165

166

P2,

N4,

P3,

N5,

P15,

P16,

P17,

N17

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

Signal Detect - Ports 0-7.

Signal Detect input from the fiber transceiver (these inputs

are only active for ports operating in fiber mode).

Logic High = Normal operation (the process of searching

for receive idles for the purpose of bringing link up is

initiated)

Logic Low = Link is declared lost

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. Tie SD[0:7] inputs to GNDPECL if unused.

Table 11. Intel® LXT9785/LXT9785E Network Interface Signal Descriptions – PQFP

Pin/Ball Designation

Symbol

Type1

Signal Description

PQFP

PBGA

107, 108

111, 110

121, 122

125, 124

136, 137

140, 139

150, 151

154, 153

T2, U1,

T3, R4,

T6, U5,

U7, T7,

T10, R10,

T11, U11,

T14,U15,

R14, T15

TPFOP0, TPFON0

TPFOP1, TPFON1

TPFOP2, TPFON2

TPFOP3, TPFON3

TPFOP4, TPFON4

TPFOP5, TPFON5

TPFOP6, TPFON6

TPFOP7, TPFON7

AO/AI

Twisted-Pair/Fiber Outputs2, Positive &

Negative, Ports 0-7.

During 100BASE-TX or 10BASE-T operation,

TPFO pins drive 802.3 compliant pulses onto

the line.

During 100BASE-FX operation, TPFO pins

produce differential LVPECL outputs for fiber

transceivers.

104, 105

115, 114

118, 119

129, 128

132, 133

143, 142

146, 147

157, 156

R2, T1,

U3, T4,

R6, T5,

T8, R8,

T9, U9,

U13, T12,

R12, T13,

R16, T16

TPFIP0, TPFIN0

TPFIP1, TPFIN1

TPFIP2, TPFIN2

TPFIP3, TPFIN3

TPFIP4, TPFIN4

TPFIP5, TPFIN5

TPFIP6, TPFIN6

TPFIP7, TPFIN7

AI/AO

Twisted-Pair/Fiber Inputs3, Positive &

Negative, Ports 0-7.

During 100BASE-TX or 10BASE-T operation,

TPFI pins receive differential 100BASE-TX or

10BASE-T signals from the line.

During 100BASE-FX operation, TPFI pins

receive differential LVPECL inputs from fiber

transceivers.

1. Type Column Coding: AI = Analog Input, AO = Analog Output.

2. Switched to Inputs (see TPFIP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

3. Switched to Outputs (see TPFOP/N description) when not in fiber mode and MDIX is not active [that is,

twisted-pair, non-crossover MDI mode].

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