LXT9785 datasheet(42/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

PAUSE

I, ID, ST

Pause Default.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 4.10 for

all ports. This register bit can be read and overwritten

after startup / reset.

When High, the LXT9785/9785E advertises Pause

capabilities on all ports during auto-negotiation.

This pin is shared with RMII-RxER1. An external pull-

up resistor (see applications section for value) can be

used to set Pause active while RxER1 is three-stated

during H/W reset. If no pull-up is used, the default

Pause state is set inactive via the internal pull-down

resistor.

174

L14

PWRDWN

I, ST, ID

Power-Down.

When High, forces the LXT9785/9785E into global

power-down mode.

Pin is not on JTAG chain.

175

M15

RESET

I, ST, IP

Reset.

This active low input is ORed with the control register

Reset Register bit 0.15. When held Low, all outputs are

forced to inactive state.

Pin is not on JTAG chain.

L4,

M2,

M3,

N1,

ADD_4

ADD_3

ADD_2

ADD_1

ADD_0

I, ST, ID

Address <4:0>.

Sets base address. Each port adds its port number

(starting with 0) to this address to determine its PHY

address.

Port 0 Address = Base

Port 1 Address = Base + 1

Port 2 Address = Base + 2

Port 3 Address = Base + 3

Port 4 Address = Base + 4

Port 5 Address = Base + 5

Port 6 Address = Base + 6

Port 7 Address = Base + 7

178

177

L17,

L16

MODESEL_1

MODESEL_0

I, ST, ID

Mode Select[1:0].

00 = RMII

01 = SMII

10 = SS-SMII

11 = Reserved

All ports are configured the same. Interfaces cannot be

mixed and must be all RMII, SMII, or SS-SMII.

176

L15

SECTION

I, ST, ID

Sectionalization Select.

This pin selects sectionalization into separate ports.

0 = 1x8 ports,

1 = 2x4 ports

Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 2 of 4)

Pin/Ball

Designation

Symbol

Type1

Signal Description2

PQFP

PBGA

1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =

Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal

Pull-Down.

2. The IP/ID resistors are disabled during hardware power-down mode.

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