LXT9785 datasheet(35/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

D8,

TxData3_0

TxData3_1

I, ID

Transmit Data - Port 3.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 3 are clocked in synchronously to REFCLK.

A11,

C10

TxData4_0

TxData4_1

I, ID

Transmit Data - Port 4.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 4 are clocked in synchronously to REFCLK.

B13,

D11

TxData5_0

TxData5_1

I, ID

Transmit Data - Port 5.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 5 are clocked in synchronously to REFCLK.

D13,

A16

TxData6_0

TxData6_1

I, ID

Transmit Data - Port 6.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 6 are clocked in synchronously to REFCLK.

203

204

E14,

C16

TxData7_0

TxData7_1

I, ID

Transmit Data - Port 7.

Inputs containing 2-bit parallel di-bits to be transmitted

from port 7 are clocked in synchronously to REFCLK.

202

E3,

B2,

C6,

A7,

B11,

A14,

C14,

D16

TxEN0

TxEN1

TxEN2

TxEN3

TxEN4

TxEN5

TxEN6

TxEN7

I, ID

Transmit Enable - Ports 0-7.

Active High input enables respective port transmitter.

This signal must be synchronous to the REFCLK.

C2,

RxData0_0

RxData0_1

O, TS

O, TS, ID

Receive Data - Port 0.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

A3,

RxData1_0

RxData1_1

O, TS

O, TS, ID

Receive Data - Port 1.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

B6,

RxData2_0

RxData2_1

O, TS

O, TS, ID

Receive Data - Port 2.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

D9,

RxData3_0

RxData3_1

O, TS

O, TS, ID

Receive Data - Port 3.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

A13,

C12

RxData4_0

RxData4_1

O, TS

O, TS, ID

Receive Data - Port 4.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

B14,

B15

RxData5_0

RxData5_1

O, TS

O, TS, ID

Receive Data - Port 5.

Receive data signals (2-bit parallel di-bits) are driven

synchronously to REFCLK.

Table 5. Intel® LXT9785/LXT9785E RMII Signal Descriptions – PQFP (Sheet 2 of 3)

Pin-Ball

Designation

Symbol

Type1

Signal Description2,3

PQFP

PBGA

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

3. RxData[0:7]_0, RxData[0:7]_1, CRS_DV[0:7] and RxER[0:7] outputs are three-stated in Isolation and H/W

Power-Down modes and during H/W reset.

LXT9785 Datasheet(PDF) 35 Page - Intel Corporation

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