LXT9785 datasheet(88/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Table 32. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – BGA23 (Sheet 1 of 4)

Ball/Pin

Designation

Symbol

Type1

Signal Description2

BGA23

PQFP

N3,

TxSLEW_0

TxSLEW_1

I, ST, ID

Tx Output Slew Controls 0 and 1 Defaults.

These pins are read at startup or reset. Their value at

that time is used to set the default state of Register bits

27.11:10 for all ports. These register bits can be read

and overwritten after startup / reset.

These pins select the TX output slew rate for all ports

(rise and fall time) as follows:

TxSLEW_1 TxSLEW_0

Slew Rate (Rise and Fall

Time)

3.3 ns

3.6 ns

3.9 ns

4.2 ns

PAUSE

ID, I, ST

Pause Default.

This pin is read at startup or reset. Its value at that time

is used to set the default state of Register bit 4.10 for

all ports. This register bit can be read and overwritten

after startup / reset.

When High, the LXT9785/9785E advertises Pause

capabilities on all ports during auto-negotiation.

This pin is shared with RMII-RxER1. An external pull-

up resistor (see applications section for value) can be

used to set Pause active while RxER1 is three-stated

during H/W reset. If no pull-up is used, the default

Pause state is set inactive via the internal pull-down

resistor.

L14

174

PWRDWN

I, ST, ID

Power-Down.

When High, forces the LXT9785/9785E into global

power-down mode.

Pin is not on JTAG chain.

M15

175

RESET

I, ST, IP

Reset.

This active low input is ORed with the control register

Reset Register bit 0.15. When held Low, all outputs are

forced to inactive state.

Pin is not on JTAG chain.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS =

Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal

Pull-Down.

2. The IP/ID resistors are disabled during hardware power-down mode.

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