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LXT9785 Datasheet(PDF) 41 Page - Intel Corporation |
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LXT9785 Datasheet(HTML) 41 Page - Intel Corporation |
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41 / 226 page ![]() LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers Datasheet 43 Document Number: 249241 Revision Number: 007 Revision Date: August 28, 2003 Table 12. Intel® LXT9785/LXT9785E JTAG Test Signal Descriptions – PQFP Pin/Ball Designation Symbol Type1 Signal Description2,3 PQFP PBGA 167 N14 TDI I, ST, IP Test Data Input. Test data sampled with respect to the rising edge of TCK. 168 N15 TDO O, TS Test Data Output. Test data driven with respect to the falling edge of TCK. 169 N16 TMS I, ST, IP Test Mode Select. 170 M16 TCK I, ST, ID Test Clock. Clock input for JTAG test. 171 M17 TRST I, ST, IP Test Reset. Reset input for JTAG test. 1. Type Column Coding: I = Input, O = Output, OD = Open Drain, TS = Three-State-able output, SMT = Schmitt Triggered input, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull- Down. 2. The IP/ID resistors are disabled during H/W Power-Down mode. If a pin is an output or an I/O, the IP/ID resistors are also disabled when the output is enabled. 3. TDO output is three-stated in H/W Power-Down mode and during H/W reset. Table 13. Intel® LXT9785/LXT9785E Miscellaneous Signal Descriptions – PQFP (Sheet 1 of 4) Pin/Ball Designation Symbol Type1 Signal Description2 PQFP PBGA 94 93 N3, M4 TxSLEW_0 TxSLEW_1 I, ST, ID Tx Output Slew Controls 0 and 1 Defaults. These pins are read at startup or reset. Their value at that time is used to set the default state of Register bits 27.11:10 for all ports. These register bits can be read and overwritten after startup / reset. These pins select the TX output slew rate for all ports (rise and fall time) as follows: TxSLEW_1 TxSLEW_0 Slew Rate (Rise and Fall Time) 0 0 3.3 ns 0 1 3.6 ns 1 0 3.9 ns 1 1 4.2 ns 1. Type Column Coding: I = Input, O = Output, OD = Open Drain Output, ST = Schmitt Triggered Input, TS = Three-State-able Output, SL = Slew-rate Limited Output, IP = Weak Internal Pull-Up, ID = Weak Internal Pull-Down. 2. The IP/ID resistors are disabled during hardware power-down mode. |
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