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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Table 8. Intel® LXT9785/LXT9785E SS-SMII Specific Signal Descriptions – PQFP

Pin/Ball

Designation

Symbol

Type1

Signal Description2,3

PQFP

PBGA

204

A6,

C16

TxSYNC0

TxSYNC1

I, ID

SS-SMII Transmit Synchronization.

The MAC must generate a TxSYNC pulse every 10 TxCLK

cycles to mark the start of TxData segments. TxSYNC0 is

used when 1x8 port sectionalization is selected.

E4,

B12

RxSYNC0

RxSYNC1

O, TS,

SS-SMII Receive Synchronization.

The LXT9785/9785E generates these pulses every 10

RxCLK cycles to mark the start of RxData segments for the

MAC. RxSYNC1 is used when 1x8 port sectionalization is

selected. RxSYNC0 may not be used. These outputs are

only enabled when SS-SMII mode is enabled.

201

C8,

D17

TxCLK0

TxCLK1

I, ID

SS-SMII Transmit Clock.

The MAC sources this 125 MHz clock as the timing

reference for TxData and TxSYNC. Only TxCLK0 is used

when 1x8 port sectionalization is selected. See “Clock/

SYNC Requirements” on page 125 for detailed clock

requirements.

E3,

B11

RxCLK0

RxCLK1

O, TS,

SS-SMII Receive Clock.

The LXT9785/9785E generates these clocks, based on

REFCLK, to provide a timing reference for RxData and

RxSYNC to the MAC. RxCLK1 is used when 1x8 port

sectionalization is selected. RxCLK0 may not be used. See

“Clock/SYNC Requirements” on page 125 for detailed clock

requirements. These outputs are only enabled when SS-

SMII mode is enabled.

205

197

B1,

B4,

C7,

B9,

C12,

B15,

B17,

F14

RxData0

RxData1

RxData2

RxData3

RxData4

RxData5

RxData6

RxData7

O, TS,

Receive Data - Ports 0-7.

These serial output streams provide data received from

the network. The LXT9785/9785E drives the data out

synchronously to REFCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode. If a Pin is an output or an I/O, the IP/ID

resistors are also disabled when the output is enabled.

3. RxData[0:7], RxSYNC[0:1], and RxCLK[0:1] outputs are three-stated in Isolation and H/W Power-Down

modes and during H/W reset.

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