LXT9785 datasheet(83/226 Pages) INTEL

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LXT9785 and LXT9785E Advanced 8-Port 10/100 Mbps PHY Transceivers

Datasheet

Document Number: 249241

Revision Number: 007

Revision Date: August 28, 2003

Table 25. Intel® LXT9785/LXT9785E SMII / SS-SMII Common Signal Descriptions – BGA23

Ball/Pin

Designation

Symbol

Type1

Signal Description2

BGA23

PQFP

E2,

C3,

B5,

D8,

A11,

B13,

D13,

E14

203

TxData0

TxData1

TxData2

TxData3

TxData4

TxData5

TxData6

TxData7

I, ID

Transmit Data - Ports 0-7.

These serial input streams provide data to be transmitted to

the network. The LXT9785/9785E clocks the data in

synchronously to REFCLK.

E6,

E12

REFCLK0

REFCLK1

Reference Clock.

The LXT9785/9785E always requires a 125 MHz reference

clock input. Refer to Functional Description for detailed clock

requirements. REFCLK0 and REFCLK1 are always

connected regardless of sectionalization mode.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

Table 26. Intel® LXT9785/LXT9785E SMII Specific Signal Descriptions – BGA23

Pin/Ball

Designation

Symbol

Type1

Signal Description2,3

BGA23

PQFP

A6,

C16

204

SYNC0

SYNC1

I, ID

SMII Synchronization.

The MAC must generate a SYNC pulse every 10 REFCLK

cycles to synchronize the SMII. SYNC0 is used when 1x8

port sectionalization is selected. SYNC0 and SYNC1 are

to be used when 2x4 port sectionalization is chosen.

C2,

A3,

B6,

D9,

A13,

B14,

C15,

E16

206

198

RxData0

RxData1

RxData2

RxData3

RxData4

RxData5

RxData6

RxData7

O, TS

Receive Data - Ports 0-7.

These serial output streams provide data received from

the network. The LXT9785/9785E drives the data out

synchronously to RXCLK.

1. Type Column Coding: I = Input, O = Output, OD = Open Drain output, ST = Schmitt Triggered input, TS =

Three-State-able output, SL = Slew-rate Limited output, IP = weak Internal Pull-up, ID = weak Internal pull-

Down.

2. The IP/ID resistors are disabled during H/W Power-Down mode.

3. RxData[0:7] outputs are three-stated in Isolation and hardware power-down modes and during hardware

reset.

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