TMPR4925 datasheet(399/590 Pages) TOSHIBA

399 / 590 page

Chapter 12 Timer/Counter

12-11

12.4.2

Timer Interrupt Status Register n (TMTISRn)

TMTISR0

0xF004

TMTISR1

0xF104

TMTISR2

0xF204

: Type

: Initial value

432

TWIS TPIBS TPIAS

TIIS

R/W0C R/W0C R/W0C R/W0C : Type

: Initial value

Bits

Mnemonic

Field Name

Description

31:4



Reserved



TWIS

Watchdog Timer

Status

Watchdog Timer TMCPRA Match Status (Initial value: 0, R/W0C)

(This bit is Reserved in the case of the TMTISR0 Register and the TMTISR1 Register.)

When in the Watchdog Timer mode, this bit is set when the counter value matches

Compare Register 2 (TMCPRA2).

This bit is cleared by writing a “0” to it.

During Read

0: Did not match the Compare Register

1: Matched the Compare Register

During Write

0: Negate interrupt

1: Invalid

2TPIBS

Pulse Generator

TMCPRB Status

Pulse Generator TMCPRB Match Status (Initial value: 0, R/W0C)

(This bit is Reserved in the case of the TMTISR2 Register.)

When in the Pulse Generator mode, this bit is set when the counter value matches

Compare Register Bn (TMCPRBn).

This bit is cleared by writing a “0” to it.

During Read

0: Did not match the Compare Register

1: Matched the Compare Register

During Write

0: Clear

1: Invalid

TPIAS

Pulse Generator

TMCPRA Status

Pulse Generator TMCPRA Match Status (Initial value: 0, R/W0C)

(This bit is Reserved in the case of the TMTISR2 Register.)

When in the Pulse Generator mode, this bit is set when the counter value matches

Compare Register A n (TMCPRAn).

This bit is cleared by writing a “0” to it.

During Read

0: Did not match the Compare Register

1: Matched the Compare Register

During Write

0: Clear

1: Invalid

TIIS

Interval Timer

TMCPRA Status

Interval Timer TMCPRA Match Status (Initial value: 0, R/W0C)

When in the Interval Timer mode, this bit is set when the counter value matches

Compare Register A n (TMCPRAn).

This bit is cleared by writing a “0” to it.

During Read

0: Did not match the Compare Register

1: Matched the Compare Register

During Write

0: Clear

1: Invalid

Figure 12.4.2 Timer Interrupt Status Register

TMPR4925 Datasheet(PDF) 399 Page - Toshiba Semiconductor

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