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TMPR4925 Datasheet(PDF) 403 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 403 Page - Toshiba Semiconductor |
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403 / 590 page ![]() Chapter 12 Timer/Counter 12-15 12.4.6 Divide Register n (TMCCDRn) TMCCDR0 0xF020 TMCCDR1 0xF120 TMCCDR2 0xF220 31 16 0 : Type : Initial value 15 32 0 0CCD R/W : Type 000 : Initial value Bits Mnemonic Field Name Description 31:3 Reserved 2:0 CCD Counter Clock Divide Value Counter Clock Divide (Initial value: 000, R/W) These bits specify the divide value when using the internal clock (IMBUSCLK) as the counter input clock source. The binary value n is divided by 2 n+1. 000: Divide by 2 1 (f/2) 001: Divide by 2 2 (f/4) 010: Divide by 2 3 (f/8) 011: Divide by 2 4 (f/16) 100: Divide by 2 5 (f/32) 101: Divide by 2 6 (f/64) 110: Divide by 2 7 (f/128) 111: Divide by 2 8 (f/256) Figure 12.4.6 Divide Register |
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