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TMPR4925 Datasheet(PDF) 410 Page - Toshiba Semiconductor |
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TMPR4925 Datasheet(HTML) 410 Page - Toshiba Semiconductor |
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410 / 590 page  Chapter 13 Parallel I/O Port 13-4 13.4.3 PIO Direction Control Register (PIODIR) 0xF508 31 16 PDIR R/W : Type 0x0000 : Initial value 15 0 PDIR R/W : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31 :0 PDIR [31:0] Direction Control Port Direction Control [31:0] (Initial value: 0x0000_0000, R/W) Sets the I/O direction of the PIO pin (PIO [31:0]). 0: Input (Reset) 1: Output Figure 13.4.3 PIO Direction Control Register 13.4.4 PIO Open Drain Control Register (PIOOD) 0xF50C 31 16 POD R/W : Type 0x0000 : Initial value 15 0 POD R/W : Type 0x0000 : Initial value Bits Mnemonic Field Name Description 31 :0 POD [31:0] Open Drain Control Port Open Drain Control [31:0] (Initial value: 0x0000_0000, R/W) Sets whether to use the PIO pin (PIO [31:0]) as an open drain. 0: Open drain (Reset) 1: Totem pole Figure 13.4.4 PIO Open Drain Control Register |
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