TMPR4925 datasheet(491/590 Pages) TOSHIBA

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Chapter 16 CHI Module

16-9

16.3.6

Interrupts

The CHI module has eight types interrupt sources.

OR signal of them connects to the internal

Interrupt Controller (IRC). Please check CHI Interrupt Status Register (CHIINT) to know which type

of interrupt occurred.

Type

Status Bits

Mask-able Bit

CHIBUSERROR

BUSI

BUSIE

CHI0_5

05I

05IE

CHI1_0

10I

10IE

CHIDMACNT

DCI

DCIE

CHIININTA

INAI

INAIE

CHIININTB

INBI

INBIE

CHIACT

ACTI

ACTIE

CHIERR

ERRI

ERRIE

CHIBUSERRORINT:

Issues an interrupt whenever the CHI DMA has bus error.

CHI0_5INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the halfway point.

CHI1_0INT:

Issues an interrupt whenever the CHI DMA buffer pointer has reached the end-of-buffer point.

CHIDMACNTINT:

Issues an interrupt each time the CHI DMA buffer pointer is incremented, which occurs whenever a

new CHI sample is read from and/or written to the CHI DMA buffer.

CHIININTA:

Issues an interrupt whenever a valid CHI input sample is available from CHI RX Holding Register A;

this also means a valid CHI output sample can be written to CHI TX Holding Register A.

CHIININTB:

Issues an interrupt whenever a valid CHI input sample is available from CHI RX Holding Register B;

this also means a valid CHI output sample can be written to CHI TX Holding Register B.

CHIACTINT:

Issues an interrupt whenever CHICLK is active. This is used for CHI wakeup purposes.

CHIERRINT:

Issues an interrupt whenever a CHI error is received. This interrupt is triggered if CPU or DMA

reading of the CHI RX Holding Registers does not keep up with the hardware filling of the CHI RX

Holding Registers or if CPU or DMA writing of the CHI TX Holding Registers does not keep up with

the hardware emptying of the CHI TX Holding Registers.

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