TMPR4925 datasheet(488/590 Pages) TOSHIBA

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Chapter 16 CHI Module

16-6

16.3.4

DMA Address Generation

The CHI Module provides support for 2 full-duplex DMA channels: receive and transmit. The circuit

used to generate the DMA address, as well as half-buffer and end-of-buffer interrupts is shown in

Figure 16.3.3.

Figure 16.3.3 CHI DMA Address Generation

The DMA buffer size is programmable (from a minimum of 16bytes up to a maximum of 16 Kbytes)

and the receive and transmit buffer start addresses are also programmable (anywhere over the full 32-bit

address space). Because there are separate start addresses, the receive and transmit buffers can be

configured to either reside in different memory spaces or share the same memory space. But in the

loopback mode, it can only share the same memory space and this ordering allows a receive-to-transmit

immediate via the DMA buffer. Thus, received samples are written to the DMA buffer location

immediately after transmit samples were read from that same location (which then became immediately

available). This ordering allows a single circular DMA buffer to be used for both transmit and receive

samples.

The DMA buffers can be configured in a circular buffer mode or a one-time buffer mode. For the

circular mode, the DMA address is continuously incremented (each time a DMA acknowledge is

received from the TX4925’s central DMA controller) and rolls over back to the start address after the

end-of-buffer is reached and will continue operating in a continuous and circular manner. For the one-

time mode, the DMA logic will stop executing whenever the end-of-buffer is reached.

Because the CHI Module reads and writes a byte at a time between the shift registers and the 32 bit

holding registers, the software must pack and unpack these bytes to and from the 32 bit words in

memory in order to multiplex and demultiplex each channel for processing. Table 16.3.1 shows the

format and organization of the CHI channels within memory for DMA mode. Consecutive byte samples

for a given channel reside in memory every 8th byte.

Half-buffer

Interrupt

One-time VS.

Circular mode

End-of-buffer

Interrupt

DMA

Control from CPU

DMA ADDR

Start

ADDR

DMA RD/WR mode

CLK

Start

ADDR

2:1

DMA

CNTL

REG

CNT

Load

Logic

Buffer

Size

CMP

ADDR CNT

÷ 2

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