TMPR4925 datasheet(486/590 Pages) TOSHIBA

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Chapter 16 CHI Module

16-4

16.3.2

Receiver

For the CHI receive direction, Buffer-A and Buffer-B receive holding registers are read either by the

DMA circuit or directly by the CPU. Each of these 2 holding registers are 32 bits wide, and CHI control

logic determines which byte to which holding register gets loaded at a given time from the 8-bit receive

shift register. In addition, the byte data loaded from the shift register to the holding register can be

MSB-first or LSB-first. Similar to the transmit direction, the receive section also operates in a ping-

pong fashion, allowing one buffer to be read (via the DMA or CPU) while the other buffer is being

loaded from the shift register a byte at a time, depending on which timeslots are active.

The receive TDM switch control register (independent from the transmit TDM switch control

timeslot.

An interrupt is available whenever a valid 32 bit word is available from the receive data holding

receive data holding register B. This also means a valid CHI output sample can be written to the

transmit data holding register B.

16.3.3

Clock and Control Generation

The CHI Module contains several programmable counters which are used to generate the various

CHI internal and external control signals and clocks. See Figure 16.3.3 for a block diagram of the CHI

clock and control generation circuit. As mentioned previously, CHICLK can be configured as either an

output (master mode) or input (slave mode). As an output, CHICLK is derived by dividing down from

IMBUSCLKF. In this mode, all CHI clocks are then synchronously locked to the main TX4925 system

clock. As an input, CHICLK is generated from an external clock source, which is asynchronous with

respect to IMBUSCLKF. The TX4925 CHI Module utilizes a digital-PLL circuit to stay “locked” to the

external source, while still operating internally using IMBUSCLKF CHIDIN and CHIDOUT are also

synchronized between IMBUSCLKF and the externally-supplied CHICLK.

CHIFS can also be configured as either an output (master mode) or input (slave mode). As an output,

CHIFS is derived by dividing down from CHICLK. For this mode, the CHIFS pulse width and polarity

is also programmable. As an input, CHIFS is generated from an external sync source. The TX4925 CHI

Module utilizes a digital-PLL circuit to stay “locked” to the external sync source, while still operating

internally using IMBUSCLKF.

The programmable receive and transmit sync delay counters shown in See Figure 16.3.2 are used to

implement the bit offset feature described earlier. The bit offset control bits determine the number of

clock cycles between the start of timeslot 0 and CHIFS. The receive and transmit sync delay counters

are independent from each other, such that the receive and transmit serial data streams can have

different bit offsets.

The programmable receive channel counter output is constantly compared with the receive TDM

switch control register values, and whenever a match occurs, the byte of data is loaded from the receive

shift register into the correct field within the receive holding register. Similarly, the programmable

transmit channel counter output is constantly compared with the transmit TDM switch control register

values, and whenever a match occurs, the byte of data is loaded from the correct field within the

transmit holding register into the receive shift register.

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