TMPR4925 datasheet(489/590 Pages) TOSHIBA

489 / 590 page

Chapter 16 CHI Module

16-7

Note that the byte lanes are swapped between the little- and big-endian modes. In the little-endian

mode, bits 31:24 of a word on the DMA buffer correspond to the byte lane with the address offset ‘+3’

and therefore to the ‘byte0’ in the CHI TX/RX holding register. On the contrary, in the big-endian

mode, bits 31:24 of a word on the DMA buffer correspond to the byte lane with the address offset ‘+0’

and therefore to the ‘byte3’ in the CHI TX/RX holding register.

Table 16.3.1 CHI DMA Memory Organization

(Relative)

Memory

Address

+0x0

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 0

+0x4

buffB, byte3

buffB, byte2

buffB, byte1

buffB, byte0

sample 0

+0x8

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 1

+0xC

buffB, byte3

buffB, byte2

buffB, byte1

buffB, byte0

sample 1

+0x10

buffA, byte3

buffA, byte2

buffA, byte1

buffA, byte0

sample 2

etc.

For a given channel, the minimum input-to-output latency for the CHI data path is (4 cycles)

(62.5

µs) = 250 µs, assuming an 8 kHz frame rate. These required 4 cycles are as follows:

•

1 cycle to load receive shift register into receive holding register

•

1 cycle for DMA of receive holding register data into receive memory space

(insert here any application-specific time required for processing of received data and moving

result to transmit memory space)

•

1 cycle for DMA of data in transmit memory space to transmit holding register

•

1 cycle to load transmit holding register data into transmit shift register

Half-buffer and end-of-buffer DMA address counter interrupts are available, allowing the CPU to

minimize overhead and utilize the DMA buffer in a ping-pong fashion. For transmit mode, the CPU can

use these interrupts to fill or write one half of the buffer while the other half is being emptied by the

DMA controller for transmitting out the CHI. Similarly, for receive mode, the CPU can use these

interrupts to empty or read one half of the buffer while the other half is being filled by the DMA

controller from received CHI input samples.

Also available is a direct CPU read/write mode for bypassing the DMA, allowing the CPU to read or

write the CHI data on a sample by sample basis, if so desired. Separate DMA enables for receive and

transmit allow DMA to be setup for receive only (transmit via CPU), transmit only (receive via CPU),

receive and transmit, or none (receive and transmit via CPU).

The DMA circuit also provides an interrupt each time the DMA buffer pointer is incremented, which

occurs whenever a new sample is read from and/or written to the DMA buffer. This interrupt may be

useful for triggering a read of the DMA pointer status value, which is the actual 12-bit DMA address

counter output. This value indicates exactly where the current address is pointing to in the overall DMA

buffer.

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