TMPR4925 datasheet(500/590 Pages) TOSHIBA

500 / 590 page

Chapter 16 CHI Module

16-18

16.4.1

CHI Control Register (CTRL)

0xA800

Reserved

LOOP TEST

FDIR

FWID

CHAN

TBOF

R/W

: Type

00000

0000

: Initial value

RBOF

TMSB RMSB RFPL TFPL REDG TEDG FEDG TFED

C2X

REN

TEN

CEN

R/W

R/W : Type

0000

: Initial value

Bits

Mnemonic

Field Name

Description

31:30



Reserved



LOOP

CHILOOP

CHILOOP bit (Initial value: 0, R/W)

This bit is used for IC testing and should not be set. Setting this bit to a logic “1”

will cause the CHI serial transmitted data to be internally looped back to the CHI

serial receive data path. The data is inverted when this mode is selected. Clearing

this bit to a logic “0” selects the normal CHIDIN pin as the CHI serial receive data

source.

TEST

CHIENTEST

CHIENTEST bit (Initial value: 0, R/W)

This bit is used for IC testing and should not be set.

FDIR

CHIFSDIR

CHIFSDIR bit (Initial value: 0, R/W)

This bit controls the direction of the CHIFS pin.

0: CHIFS to be an input.(CHI sync slave mode) Note*

1: CHIFS to be an output.(CHI sync master mode)

Note that CHIRXFSPOL and CHIFSEDGE bits must be set to proper values even

when CHIFSDIR is set to a logic “1” (CHI sync master mode).

26:25

FWID[1:0]

CHIFSWIDTH

CHIFSWIDTH bits (Initial value: 00, R/W)

These bits are used to select pulse width for the CHIFS signal, relevant whenever

the CHI Module is configured as master mode. The pulse width is counted by data

bit width. (In clk2x mode, two CHICLKs correspond to one data bit.) The available

CHIFS pulse widths are as follows

00: 1 bit wide

01: 2 bits wides

10: 1 byte wide

11: half-frame wide

24:20

CHAN[4:0]

CHINCHAN

CHINCHAN bits (Initial value: 00000, R/W)

These bits are used to program the number of 8-bit channel timeslots per half-

frame, up to 32 total per half-frame. The value loaded for CHINCHAN is the

desired number of channels-1.

19:16

TBOF[3:0]

CHTXBOFF

CHITXBOFF bits (Initial value: 0000, R/W)

These bits select the transmit data programmable bit offset, which is related to the

number of clocks from the start of timeslot 0 (1st timeslot) transmit data to the

CHIFS edge used to trigger the start of each CHI frame. The value loaded for

CHITXBOFF must be chosen from Table 16.3.3 according to the configuration.

15:12

RBOF[3:0]

CHIRXBOFF

CHIRXBOFF bits (Initial value: 0000, R/W)

These bits select the receive data programmable bit offset, which is related to the

number of clocks from the start of timeslot 0 (1st timeslot) receive data to the

CHIFS edge used to trigger the start of each CHI frame. The value loaded for

CHIRXBOFF must be chosen from Table 16.3.2 according to the configuration.

TMSB

TXMSBFIRST

TXMSBFIRST bit (Initial value: 0, R/W)

This bit selects between MSB-first and LSB-first serial data formats for each byte

of the CHI transmit data.

0: LSB-first

1: MSB-first

Figure 16.4.1 Control Register (CTRLREG) (1/3)

TMPR4925 Datasheet(PDF) 500 Page - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 500 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL