TMPR4925 datasheet(501/590 Pages) TOSHIBA

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Chapter 16 CHI Module

16-19

Bits

Mnemonic

Field Name

Description

RMSB

RXMSBFIRST

RXMSBFIRST bit (Initial value: 0, R/W)

This bit selects between MSB-first and LSB-first serial data formats for each byte

of the CHI receive data.

0: LSB-first

1: MSB-first

9RFPL

CHIRXFSPOL

CHIRXFSPOL bit (Initial value: 0, R/W)

This bit selects between positive (active high) or negative (active low) polarity for

the received CHIFS signal pulse. This bit must be properly set in CHI sync master

mode, as well as in CHI sync slave mode; In CHI sync master mode,

CHIRXFSPOL must be equal to CHITXFSPOL.

0: positive polarity for the CHIFS pulse. (the rising edge of the CHIFS pulse is

used to trigger the start of the CHI frame period.)

1: negative polarity for the CHIFS pulse. ( the falling edge of the CHIFS pulse is

used to trigger the start of the CHI frame period.)

TFPL

CHITXFSPOL

CHITXFSPOL bit (Initial value: 0, R/W)

This bit selects between positive (active high) or negative (active low) polarity for

the transmitted CHIFS signal pulse, relevant whenever the CHI Module is

configured as master mode.

0: positive polarity for the CHIFS pulse

1: negative polarity for the CHIFS pulse

7REDG

CHIRXEDGE

CHIRXEDGE bit (Initial value: 0, R/W)

This bit selects whether to use either the rising edge or falling edge of CHICLK to

sample the receive data CHIDIN. CHIDIN must be stable before and after the

specified CHICLK edge.

0: falling edge

1: rising edge

6TEDG

CHITXEDGE

CHITXEDGE bit (Initial value: 0, R/W)

This bit selects whether to use either the rising edge or falling edge of CHICLK to

clock out the transmit data CHIDOUT.

0: falling edge

1: rising edge

5FEDG

CHIFSEDGE

CHIFSEDGE bit (Initial value: 0, R/W)

This bit selects whether to use either the rising edge or falling edge of CHICLK to

sample the receive frame sync CHIFS. This bit must be properly set in CHI sync

master mode, as well as in CHI sync slave mode. CHIFS must be stable before

and after the specified CHICLK edge; In CHI sync master mode, CHIFSEDGE

must be equal to inverted CHITXFSEDGE.

0: falling edge

1: rising edge

TFED

CHITXFSEDGE

CHITXFSEDGE (Initial value: 0, R/W)

This bit selects whether to use either the rising edge or falling edge of CHICLK to

clock out the transmit frame sync CHIFS, relevant whenever the CHI Module is

configured as master mode.

0: falling edge

1: rising edge

3C2X

CHICLK2XMODE

CHICLK2XMODE bit (Initial value: 0, R/W)

This bit selects between 1x and 2x clock modes.

0: 1x clock mode (CHICLK frequency equals the serial data bit rate)

1: 2x clock mode (CHICLK frequency equals twice the serial data bit rate)

2REN

CHIRXEN

CHIRXEN bit (Initial value: 0, R/W)

This bit is used to enable/disable CHI receive processing in the direct CPU

read/write mode, where the CPU reads the received data through the CHI RX

holding register.

This bit has no effect when RX DMA is enabled.

0: Disable (all received data to not be processed by the CHI module)

1: Enable

Figure 16.4.1 Control Register (CTRLREG) (2/3)

TMPR4925 Datasheet(PDF) 501 Page - Toshiba Semiconductor

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