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TMPR4925 Datasheet(PDF) 504 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 504 Page - Toshiba Semiconductor

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Chapter 16 CHI Module
16-22
Bits
Mnemonic
Field Name
Description
23
RB3E
CHIRXPTRB3EN
CHIRXPTRB3EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRB3
0: Disable
1: Enable
22
RB2E
CHIRXPTRB2EN
CHIRXPTRB2EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRB2
0: Disable
1: Enable
21
RB1E
CHIRXPTRB1EN
CHIRXPTRB1EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRB1
0: Disable
1: Enable
20
RB0E
CHIRXPTRB0EN
CHIRXPTRB0EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRB0
0: Disable
1: Enable
19
RA3E
CHIRXPTRA3EN
CHIRXPTRA3EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRA3
0: Disable
1: Enable
18
RA2E
CHIRXPTRA2EN
CHIRXPTRA2EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRA2
0: Disable
1: Enable
17
RA1E
CHIRXPTRA1EN
CHIRXPTRA1EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRA1
0: Disable
1: Enable
16
RA0E
CHIRXPTRA0EN
CHIRXPTRA0EN bit (Initial value: 0, R/W)
This bit is used to enable/disable the timeslot for the receive channel pointed to by
the TDM switch pointer CHIRXPTRA0
0: Disable
1: Enable
15:0
Reserved
Figure 16.4.2 CHI Pointer Enable Register (PNTREN) (2/2)



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