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TMPR4925 Datasheet(PDF) 513 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 513 Page - Toshiba Semiconductor

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Chapter 16 CHI Module
16-31
16.4.11 CHI RX Holding Register (CHIHOLD)
0xA824
31
16
CHIRXHOLD
R: Type
0000000000000000
: Initial value
15
0
CHIRXHOLD
R: Type
0000000000000000
: Initial value
Bits
Mnemonic
Field Name
Description
31:0
CHIHOLD[31:0]
CHIRXHOLD
CHIRXHOLD bits (Initial value: 32’b0, R)
These bits represent the CHI data to be received. CHI data can be either read
directly from this register by the CPU or transparently written to the CHI RX DMA
buffer from this register. This register should only be read by the CPU after the
CHIININTA or CHIININTB interrupt is asserted. The read immediately after
CHIININTA sees the internal RX holding register A and the read immediately after
CHIININTB sees the internal RX holding register B. Receive data for bytes 3, 2, 1,
and 0 are stored into the 32-bit CHIRXHOLD at locations [31:24], [23:16], [15:8],
and [7:0], respectively. These data bytes correspond to the CHI timeslots as defined
by the values in the RXPTRA and RXPTRB TDM switch registers.
Figure 16.4.11 CHI RX Holding Register (CHIHOLD)



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