TMPR4925 datasheet(516/590 Pages) TOSHIBA

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Chapter 16 CHI Module

16-34

16.4.14 CHI Interrupt Status Register (CHIINT)

0xA830

Reserved

: Type

: Initial value

Reserved

BUSI

05I

10I

DCI

INAI

INBI

ACTI

ERRI

R/W

: Type

00000000

: Initial value

Bits

Mnemonic

Field Name

Description

31:8



Reserved



BUSI

CHIBUSERROR

Interrupt Status

CHIBUSERROR Interrupt status bit (Initial value: 0, R/W)

This bit shows the CHIBUSERROR Interrupt Status. This bit is cleared by written

“0”.

0: No interrupt

1: Interrupt occurs

05I

CHI0_5

Interrupt Status

CHI0_5 Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHI0_5 Interrupt Status. This bit is cleared by written “0”.

0: No interrupt

1: Interrupt occurs

10I

CHI1_0

Interrupt Status

CHI1_0 Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHI1_0 Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

DCI

CHIDMACNT

Interrupt Status

CHIDMACNT Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHIDMACNT Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

INAI

CHIININTA

Interrupt Status

CHIININTA Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHIININTA Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

2INBI

CHIININTB

Interrupt Status

CHIININTB Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHIININTB Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

ACTI

CHIACTINT

Interrupt Status

CHIACTINT Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHIACTINT Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

ERRI

CHIERRINT

Interrupt Status

CHIERRINT Interrupt Status bit (Initial value: 0, R/W)

This bit shows the CHIERRINT Interrupt Status. This bit is cleared by written “0”

0: No interrupt

1: Interrupt occurs

Figure 16.4.14 CHI Interrupt Status Register (CHIINT)

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