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TMPR4925 Datasheet(PDF) 512 Page - Toshiba Semiconductor

Part # TMPR4925
Description  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4925 Datasheet(HTML) 512 Page - Toshiba Semiconductor

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Chapter 16 CHI Module
16-30
16.4.10 CHI TX Holding Register (CHIHOLD)
0xA824
31
16
CHITXHOLD
W: Type
0000000000000000
: Initial value
15
0
CHITXHOLD
W: Type
0000000000000000
: Initial value
Bits
Mnemonic
Field Name
Description
31:0
CHIHOLD[31:0]
CHITXHOLD
CHITXHOLD bits (Initial value: 32’b0, W)
These bits represent the CHI data to be transmitted. CHI data can be either written
directly to this register by the CPU or transparently read from the CHI TX DMA
buffer to this register. This register should only be loaded by the CPU after the
CHIININTA or CHIININTB interrupt is asserted. The write immediately after
CHIININTA updates the internal TX holding register A and the write immediately
after CHIININTB updates the internal TX holding register B. Transmit data for bytes
3, 2, 1, and 0 are loaded into the 32-bit CHITXHOLD at locations [31:24], [23:16],
[15:8], and [7:0], respectively. These data bytes correspond to the CHI timeslots as
defined by the values in the TXPTRA and TXPTRB TDM switch registers.
Figure 16.4.10 CHI TX Holding Register (CHIHOLD)



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